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preliminary psoc ? 4: psoc 4xx8_ble family datasheet programmable system-on-chip (psoc ? ) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-94624 rev. *l revised april 26, 2017 general description psoc ? 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an arm ? cortex?-m0 cpu. it combines programmable and reconfigurable a nalog and digital blo cks with flexible auto matic routing. the psoc 4xx8_ble product family, based on this platform, is a combinat ion of a microcontroller with an integrated bluetooth low ene rgy (ble), also known as bluetooth smart, radio and subsystem (bless). the other features include digital programmable logic, high-performance analog-to-digital conversion (adc), opamps with comparator mode, and stan dard communication and timing peripherals. the psoc 4xx8_ble products will be fully upward comp atible with members of the psoc 4 platform for new applications and design needs. the programmable analog and digital subsystem s allow flexibility and in-field tuning of the design. features 32-bit mcu subsystem 48-mhz arm cortex-m0 cpu wi th single-cycle multiply up to 256 kb of flash with read accelerator up to 32 kb of sram ble radio and subsystem 2.4-ghz rf transceiver with 50- ? antenna drive digital phy link-layer engine supporting master and slave modes rf output power: ?18 dbm to +3 dbm rx sensitivity: ?92 dbm rx current: 18.7 ma tx current: 16.5 ma at 0 dbm rssi: 1-db resolution programmable analog four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and adc input buffering capability. can operate in deep sleep mode. 12-bit, 1-msps sar adc with differential and single-ended modes; channel sequencer with signal averaging two current dacs (idacs) for ge neral-purpose or capacitive sensing applications on any pin two low-power comparators that operate in deep sleep mode programmable digital four programmable logic blocks ca lled universal digital blocks, (udbs), each with eight macrocells and data path cypress-provided peripheral component library, user-defined state machines, and verilog input power management active mode: 1.7 ma at 3-mhz flash program execution deep sleep mode: 1.3 a with watch crystal oscillator (wco) on hibernate mode: 150 na with ram retention stop mode: 60 na capacitive sensing cypress capacitive sigma-delta (csd) provides best-in-class snr (>5:1) and liquid tolerance cypress-supplied software co mponent makes capacitive sensing design easy automatic hardware tuning algorithm (smartsense?) segment lcd drive lcd drive supported on all pins (common or segment) operates in deep sleep mode with four bits per pin memory serial communication two independent run-time reconfigurable serial communi- cation blocks (scbs) with reconfigurable i 2 c, spi, or uart functionality timing and pulse-width modulation four 16-bit timer/counter pu lse-width modulator (tcpwm) blocks center-aligned, edge, and pseudo-random modes comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications up to 36 programmable gpios 7mm 7mm 56-pin qfn package 76-ball csp and thin csp packages any gpio pin can be capsense, lcd, analog, or digital two overvoltage-tolerant (ovt) pins; drive modes, strengths, and slew rates are programmable psoc creator? design environment integrated design environmen t (ide) provides schematic design entry and build (with analog and digital automatic routing) api components for all fixed-function and programmable peripherals industry-standard tool compatibility after schematic entry, development can be done with arm-based industry-stand ard development tools
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 2 of 48 more information cypress provides a wealth of data at http://www.cypress.com to help you to select the right psoc device for your design, and to help you to quickly and effectively integrate the device into your de sign. for a comprehensive list of resources, see the introducti on page for bluetooth? low energy (ble) products . following is an abbreviated list for psoc 4 ble: overview: psoc portfolio , psoc roadmap product selectors: psoc 1 , psoc 3 , psoc 4 , psoc 4 ble , psoc 5lp. in addition, psoc creator includes a device selection tool. application notes: cypress offers a large number of psoc application notes covering a bro ad range of topics, from basic to advanced level. recommended application notes for getting started with psoc 4 ble are: ? an91267 : getting started with psoc 4 ble ? an91184 : psoc 4 ble - designing ble applications ? an91162 : creating a ble custom profile ? an97060 : psoc 4 ble and proc bl e - over-the-air (ota) device firmware upgrade (dfu) guide ? an91445 : antenna design and rf layout guidelines ? an96841 : getting started with ez-ble module ? an85951 : psoc 4 capsense design guide ? an95089 : psoc 4/proc ble crystal oscillator selection and tuning techniques ? an92584 : designing for low power and estimating battery life for ble applications technical reference manual (trm) is in two documents: ? architecture trm details each psoc 4 ble functional block. ? registers trm describes each of the psoc 4 registers. development kits: ? cy8ckit-042-ble pioneer kit, is a flexible, arduino-com- patible, ble development kit for psoc 4 ble and proc ble. ? cy8ckit-142 , psoc 4 ble module, features a psoc 4 ble device, two crystals for the antenna matching network, a pcb antenna, and other passives, while providing access to all gpios of the device. ? cy8ckit-143 , psoc 4 ble 256 kb module, features a psoc 4 ble 256 kb device, two crystals for the antenna matching network, a pcb anten na, and other passives, while providing access to all gpios of the device. ? cy5676 , proc ble 256 kb module, features a proc ble 256 kb device, two crystals for the antenna matching net- work, a pcb antenna, and other passives, while providing access to all gpios of the device. the miniprog3 device provides an interface for flash programming and debug. psoc creator psoc creator is a free windows-based integrated design environment (i de). it enables concurrent hardware and firmware design of psoc 3, psoc 4, and psoc 5lp based systems. create designs usin g classic, familiar schematic capture supported by over 100 pre-verified, production-ready psoc components; see the list of component datasheets . with psoc creator, you can: 1. drag and drop component icons to build your hardware system design in the main design workspace 2. codesign your application firm ware with the psoc hardware, using the psoc creator ide c compiler 3. configure components using the configuration tools 4. explore the library of 100+ components 5. review component datasheets figure 1. multiple-sensor example project in psoc creator
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 3 of 48 contents functional definition........................................................ 5 cpu and memory subsystem ..................................... 5 system resources ...................................................... 5 ble radio and subsyst em ........... .............. ........... ..... 6 analog blocks.............................................................. 7 programmable digital.................................................. 8 fixed-function digital .................................................. 9 gpio ........................................................................... 9 special-function peripherals .. .................................. 10 pinouts ............................................................................ 11 power............................................................................... 16 development support .................................................... 17 documentation .......................................................... 17 online ........................................................................ 17 tools.......................................................................... 17 electrical specifications ................................................ 18 absolute maximum ratings..... .................................. 18 device-level specifications ...................................... 18 analog peripherals .... .............. .............. .............. ...... 23 digital peripherals .... .............. .............. .............. ....... 27 memory ..................................................................... 29 system resources .................................................... 30 ordering information...................................................... 37 ordering code definitions ...... ................................... 38 packaging........................................................................ 39 wlcsp compatibility ................................................ 41 acronyms ........................................................................ 43 document conventions ................................................. 45 units of measure ....................................................... 45 revision history ............................................................. 46 sales, solutions, and legal information ...................... 47 worldwide sales and design s upport ......... .............. 47 products .................................................................... 47 psoc? solutions ...................................................... 47 cypress developer community................................. 47 technical support .................. ................................... 47
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 4 of 48 figure 2. block diagram the psoc 4xx8_ble devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. the arm swd interface supports all programming and debug features of the device. complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. it does not require special interfaces, debugging pods, simulators, or emulators. only the standard programming connections are required to fully support debugging. the psoc creator ide provides fully integrated programming and debugging support for the psoc 4xx8_ble devices. the swd interface is fully compatible with industry-standard third-party tools. with the ability to disable debug features, very robust flash protection, and allowing customer-proprietary functionality to be implemente d in on-chip pr ogrammable blocks, the psoc 4xx8_ble family provides a level of security not possible with multi-chip application solutions or with microcon- trollers. debug circuits are enabled by default and can only be disabled in firmware. if not enabled, the only way to re-enable them is to erase the entire device, clear fl ash protection, and reprogram the device with the new firmwar e that enables debugging. additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a malicio usly reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. because all programming, debug, and test inter- faces are disabled when maximum device security is enabled, psoc 4xx8_ble with device security enabled may not be returned for failure analysis. this is a trade-off the psoc 4xx8_ble allows the customer to make. peripherals cpu subsystem system interconnect (multi layer ahb) psoc 4a-ble deepsleep hibernate active/sleep power modes digital dft test analog dft system resources power clock reset clock control imo sleep control ref por reset control wic xres wdt ilo ioss gpio (7x ports) i/o subsystem peripheral interconnect (mmio) pclk swd/tc nvic, irqmux cortex m0 48 mhz fast mul flash 256/128 kb read accelerator sram 32/16 kb sram controller rom 8 kb rom controller nvlatches pwrsys bod 32-bit ahb-lite lvd 4x tcpwm x4 udb ... programmable digital udb capsense 2x scb -i2c/spi/uart lcd 2x lp comparator port interface & digital system interconnect (dsi) 36x gpios, 2x gpio_ovt sar adc (12-bit) x1 ctbm x2 2x opamp programmable analog sarmux high speed i/o matrix bluetooth low energy subsystem ble baseband peripheral gfsk modem 2.4 ghz gfsk radio 24mhz xo ldo i/o: antenna/power/crystal 1kb sram 32khz xo
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 5 of 48 functional definition cpu and memory subsystem cpu the cortex-m0 cpu in psoc 4xx8_ble is part of the 32-bit mcu subsystem, which is optimiz ed for low-power operation with extensive clock gating. it mo stly uses 16-bit instructions and executes a subset of the thumb- 2 instruction set. this enables fully compatible binary upward migration of the code to higher-performance processors such as cortex-m3 and m4. the cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. it includes a nested vectored interrupt controller (nvic) bloc k with 32 interrupt inputs and a wakeup interrupt controller (wic). the wic can wake the processor up from the deep sleep mode, allowing power to the main processor to be switched off when the chip is in the deep sleep mode. the cortex-m0 cpu provides a nonmaskable interrupt (nmi) input, which is made available to the user when it is not in use for system functions requested by the user. the cpu also includes an swd interface, which is a 2-wire form of jtag; the debug configuration used for psoc 4xx8_ble has four break-point (address) comparators and two watchpoint (data) comparators. flash the psoc 4xx8_ble device has a flash module with either 128 kb or 256 kb of flash memory, tightly coupled to the cpu to improve average access times from the flash block. the flash block is designed to deliver 2 wait-state (ws) access time at 48 mhz and with 1-ws access time at 24 mhz. the flash accelerator delivers 85% of single-cycle sram access performance on average. part of the flash module can be used to emulate eeprom operation if required. maximum erase and program time is 20 ms per row (256 bytes). this also applies to the emulated eeprom. sram sram memory is retained during hibernate. srom the 8-kb supervisory rom contains a library of executable functions for flash programming. these functions are accessed through supervisory calls (svc) and enable in-system programming of the flash memory. system resources power system the power system is described in detail in the section power on page 16 . it provides an assurance t hat the voltage levels are as required for the respective modes, and can either delay the mode entry (on power-on reset (por), for example) until voltage levels are as required or generate resets (brownout detect (bod)) or interrupts when the power supply reaches a particular program- mable level between 1.8 and 4.5 v (low voltage detect (lvd)). psoc 4xx8_ble operates with a single external supply (1.71 to 5.5 v without radio, and 1.9 v to 5.5 v with radio). the device has five different power modes; transitions between these modes are managed by the power system. psoc 4xx8_ble provides sleep, deep sleep, hibernate, and stop low-power modes. refer to the technical reference manual for more details. clock system the psoc 4xx8_ble clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. in addition, the clock system ensures that no metastable conditions occur. the clock system for psoc 4xx8_bl e consists of the internal main oscillator (imo), the intern al low-speed oscillator (ilo), the 24-mhz external crystal oscillato r (eco) and the 32-khz watch crystal oscillator (wco). in addition, an external clock may be supplied from a pin. imo clock source the imo is the primary source of internal clocking in psoc 4xx8_ble. it is trimmed during testing to achieve the specified accuracy. trim values are stored in nonvolatile latches (nvl). additional trim settings from flash can be used to compensate for changes. the imo default frequency is 24 mhz and it can be adjusted between 3 to 48 mhz in steps of 1 mhz. the imo tolerance with cypress-provided calibration settings is 2%. ilo clock source the ilo is a very low-power oscillator, which is primarily used to generate clocks for the peripheral operation in the deep sleep mode. ilo-driven counters can be calibrated to the imo to improve accuracy. cypress provides a software component, which does the calibration. external crystal oscillator (eco) the eco is used as the active clock for the ble subsystem to meet the 50-ppm clock accuracy of the bluetooth 4.2 specification. psoc 4xx8_ble includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency. the high-accuracy eco clock can also be used as a system clock. watch crystal oscillator (wco) the wco is used as the sleep clock for the ble subsystem to meet the 500-ppm clock accuracy for the bluetooth 4.2 specification. the sleep clock provides an accurate sleep timing and enables wakeup at the specified advertisement and connection intervals. the wco output can be used to realize the real-time clock (rtc) function in firmware. watchdog timer a watchdog timer is implemented in the clock block running from the ilo or from the wco; this allows the watchdog operation during deep sleep and generates a watchdog reset if not serviced before the timeout occurs. the watchdog reset is recorded in the reset cause register. with the wco and firmware, an accurate real-time clock (within the bounds of the 32-khz crystal accuracy) can be realized.
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 6 of 48 figure 3. psoc 4xx8_ble mcu clocking architecture the hfclk signal can be divided down (see figure 3 ) to generate synchronous clocks for the udbs, and the analog and digital peripherals. there are a total of 12 clock dividers for psoc 4xx8_ble: ten with 16-bit divide capability and two with 16.5-bit divide capability. this allows the generation of 16 divided clock signals, which can be used by peripheral blocks. the analog clock leads the digital clocks to allow analog events to occur before the digital clock-related noise is generated. the 16-bit and 16.5-bit dividers allow a lot of flexibility in generating fine-grained frequency values and are fully supported in psoc creator. reset psoc 4xx8_ble device can be reset from a variety of sources including a software reset. reset events are asynchronous and guarantee reversion to a known state. the reset cause is recorded in a register, which is sticky through resets and allows the software to determine the c ause of the reset. an xres pin is reserved for an external reset to avoid complications with the configuration and multiple pin functions during power-on or reconfiguration. the xres pin has an internal pull-up resistor that is always enabled. voltage reference the psoc 4xx8_ble reference system generates all internally required references. a one-perc ent voltage reference spec is provided for the 12-bit adc. to allow better signal-to-noise ratios (snr) and better absolute accuracy , it is possible to bypass the internal reference using a gpio pin or use an external reference for the sar. refer to table 19, ?sar adc ac specifications,? on page 26 for details. ble radio and subsystem psoc 4xx8_ble incorporates a bluetooth smart subsystem that contains the physical layer (phy) and link layer (ll) engines with an embedded aes-128 security engine. the physical layer consists of the digital phy and the rf transceiver that transmits and receives gfsk packets at 1 mbps over a 2.4-ghz ism band, which is compliant with bluetooth smart bluetooth specificatio n 4.2. the baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. key protocol elements, such as hci and link control, are implemented in firmware. time-critical functional blocks, such as encryption, crc, data whitening, and access code correlation, are implemented in hardware (in the ll engine). the rf transceiver contains an integrated balun, which provides a single-ended rf port pin to drive a 50- ? antenna via a matching/filtering network. in t he receive direction, this block converts the rf signal from the antenna to a digital bit stream after performing gfsk demodulation. in the transmit direction, this block performs gfsk modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna. the bluetooth smart radio and subsystem (bless) requires a 1.9-v minimum supply (the range varies from 1.9 v to 5.5 v). key features of bless are as follows: master and slave single-mode protocol stack with logical link control and adaptation protocol (l2cap), attribute (att), and security manager (sm) protocols api access to generic attribute profile (gatt), generic access profile (gap), and l2cap l2cap connection-oriented ch annel (bluetoot h 4.1 feature) gap features ? broadcaster, observer, peripheral, and central roles ? security mode 1: level 1, 2, 3, and 4 ? security mode 2: level 1 and 2 ? user-defined advertising data ? multiple bond support gatt features ? gatt client and server ? supports gatt sub-procedures ? 32-bit universally unique identifier (uuid) (bluetooth 4.1 feature) security manager (sm) ? pairing methods: just works, passkey entry, out of band, and numeric comparison ? authenticated man-in-the-middle (mitm) protection and data signing link layer (ll) ? master and slave roles ? 128-bit aes engine ? encryption ? low-duty cycle advertisin g (bluetooth 4.1 feature) ? le ping (bluet ooth 4.1 feature) ? le data packet length extension ? link layer privacy (with extended scanning filter policy) ? le secure connections supports all sig-adopted ble profiles ? imo ilo extclk lfclk presca le r sysclk divider 0 (/16) per 0_clk divider 9 (/16) fra ction al divider 0 (/16.5) fra ction al divider 1 (/16.5) eco wco hfclk per15_clk divider /2 n (n=0..3)
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 7 of 48 analog blocks 12-bit sar adc the 12-bit, 1-msps sar adc can operate at a maximum clock rate of 18 mhz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion (up to 806 ksps for the psoc 41x8_ble derivatives). the block functionality is augmented for the user by adding a reference buffer to it (trimmable to 1%) and by providing the choice of three internal voltage references, v dd , v dd /2, and v ref (nominally 1.024 v), as we ll as an external reference through a gpio pin. the sample-and-hold (s/h) aperture is programmable; it allows the gain bandwidth requirements of the amplifier driving the sar inputs, which determine its settling time, to be relaxed if required. system performance will be 65 db for true 12-bit precision provi ded appropriate references are used and system noise levels pe rmit it. to improve the perfor- mance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. the sar is connected to a fixed set of pins through an 8-input sequencer. the sequencer cycles through the selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth is equal to 1 msps whether it is for a single channel or distributed over several channels). the sequencer switching is effected through a state machine or through firmware-driven switching. a feature provided by the sequencer is the buffering of each channel to reduce cpu interrupt-service requirements. to accommodate signals with varying source impedances and frequencies, it is possible to have different sample times programmable for each channel. also, the signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; th is allows fast detection of out-of-range values without having to wait for a sequencer scan to be completed and the cpu to read the values and check for out-of-range values in software. the sar is able to digitize the output of the on-chip temperature sensor for calibration and other temperature-dependent functions. the sar is not available in deep sleep and hibernate modes as it requires a high-speed clock (up to 18 mhz). the sar operating range is 1.71 to 5.5 v. figure 4. sar adc system diagram opamps (ctbm block) psoc 42x8_ble has four opamps with comparator modes, which allow most common analog functions to be performed on-chip, eliminating exter nal components. pgas, voltage buffers, filters, transimpedance amplifiers, and other functions can be realized with external pa ssives saving power, cost, and space. the on-chip opamps are designed with enough bandwidth to drive the sample-and-hold circuit of the adc without requiring external buffering. temperature sensor psoc 4xx8_ble has an on-chip temperature sensor. this consists of a diode, which is biased by a current source that can be disabled to save power. the temperature sensor is connected to the adc, which digitizes the reading and produces a temper- ature value by using a cypress-supplied software that includes calibration and linearization. low-power comparators psoc 4xx8_ble has a pair of low-power comparators, which can also operate in deep sleep and hibernate modes. this allows the analog syst em blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. the comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (hibernate) where the system wake-up circuit is activated by a comparator-switch event. sarmux port 3 (8 inputs) vplus vminus p0 p7 data and status flags reference selection external reference and bypass (optional ) pos neg sar sequencer saradc inputs from other ports vdd/2 vddd vref ahb system bus and programmable logic interconnect sequencing and control
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 8 of 48 programmable digital universal digital blocks (u dbs) and port interfaces the psoc 4xx8_ble has four udbs; the udb array also provides a switched digital syst em interconnect (dsi) fabric that allows signals from peripherals and ports to be routed to and through the udbs for communication and control. figure 5. udb array udbs can be clocked from a clock-divider block, from a port interface (required for peripherals such as spi), and from the dsi network directly or after synchronization. a port interface is defined, which acts as a register that can be clocked with the same source as the plds inside the udb array. this allows a faster operation because the inputs and outputs can be registered at the port interface close to the i/o pins and at the edge of the array. the port interface registers can be clocked by one of the i/os from the same port. this allows interfaces such as spi to operate at higher clock speeds by eliminating the delay for the port input to be routed over dsi and used to register other inputs (see figure 6 ). figure 6. port interface udbs can generate interrupts (one udb at a ti me) to the interrupt controller. udbs retain the ability to connect to any pin on the chip through the dsi. programmable digital subsystem udbif udb udb udb udb dsi dsi dsi dsi bus if clk if port if port if port if high -s peed i/o matrix cpu sub-system system interconnect clocks 4 to 8 8 to 32 routing channels other digital signals in chip irq if clock selector block from udb 9 digital globalclocks 3 dsi signals , 1 i/o signal 4 reset selector block from udb 2 2 input registers output registers to dsi 8 from dsi 8 8 8 enables 8 from dsi 4 4 7 6 . . . 0 7 6 . . . 0 3 2 1 0 high speed i/o matrix to clock tree [0] [0] [1] [1] [1 ] [1]
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 9 of 48 fixed-function digital timer/counter/pwm block the timer/counter/pwm block cons ists of four 16-bit counters with user-programmable period length. there is a capture register to record the count valu e at the time of an event (which may be an i/o event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as pwm duty cycle outputs. the block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary pwm outputs. it also has a kill input to force outputs to a predetermined state; for example, this is used in motor-drive systems when an overcurrent state is indicated and the pwms driving the fets need to be shut off immediately with no time for software intervention. serial communication blocks (scb) psoc 4xx8_ble has two scbs, each of which can implement an i 2 c, uart, or spi interface. i 2 c mode : the hardware i 2 c block implements a full multi-master and slave interface (it is capable of multimaster arbitration). this block is capable of operating at speeds of up to 1 mbps (fast mode plus) and has flexible buffering options to reduce the interrupt overhead and latency for the cpu. it also supports ezi 2 c that creates a mailbox address range in the memory of psoc 4xx8_ble and effectively reduces the i 2 c communication to reading from and writing to an array in the memory. in addition, the block supports an 8-deep fifo for receive and transmit, which, by increasing the time given for the cpu to read the data, greatly reduces the need for clock stretching caused by the cpu not having read the data on time. the fifo mode is available in all channels and is very useful in the absence of dma. the i 2 c peripheral is compatible with i 2 c standard-mode, fast-mode, and fast-mode plus dev ices as defined in the nxp i 2 c-bus specification and user manual (um10204). the i 2 c bus i/o is implemented with gpio in open-drain modes. scb1 is fully compliant with standard mode (100 khz), fast mode (400 khz), and fast-mode plus (1 mhz) i 2 c signaling specifications when routed to gpio pins p5[0] and p5[1], except for hot-swap capability during i 2 c active communication. the remaining gpios do not meet the hot-swap specification (v dd off; draw < 10-a current) for fast mode and fast-mode plus, i ol spec (20 ma) for fast-mode plus, hysteresis spec (0.05 v dd ) for fast mode and fast-mode pl us, and minimum fall time spec for fast mode and fast-mode plus. gpio cells, including p5.0 and p5.1, cannot be hot-swapped or powered up independent of the rest of the i 2 c system. the gpio pins p5.0 and p5.1 are over-voltage tolerant but cannot be hot-swapped or powe red up independent of the rest of the i 2 c system fast-mode plus has an i ol specification of 20 ma at a v ol of 0.4 v. the gpio cells can sink a maximum of 8 ma i ol with a v ol maximum of 0.6 v. fast-mode and fast-mode plus specify minimum fall times, which are not met with the gpio cell; the slow-strong mode can help meet this spec depending on the bus load. uart mode : this is a full-feature uart operating at up to 1 mbps. it supports automotive single-wire interface (lin), infrared interface (irda), and smar tcard (iso7816) protocols, all of which are minor variants of the basic uart protocol. in addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common rx and tx lines. common uart functions such as parity error, break detect, and frame error are supported. an 8-deep fifo allows much greater cpu service latencies to be tolerated. note that hardware handshaking is not supported. this is not commonly used and can be implemented with a udb-based uart in the system, if required. spi mode : the spi mode supports full motorola spi, ti secure simple pairing (ssp) (essentially adds a start pulse that is used to synchronize spi codecs), and national microwire (half-duplex form of spi). the spi block can use the fifo and supports an ezspi mode in which the data interchange is reduced to reading and writing an array in memory. gpio psoc 4xx8_ble has 36 gpios. the gpio block implements the following: eight drive strength modes: ? analog input mode (input and output buffers disabled) ? input only ? weak pull-up with strong pull-down ? strong pull-up with weak pull-down ? open drain with strong pull-down ? open drain with strong pull-up ? strong pull-up with strong pull-down ? weak pull-up with weak pull-down input threshold select (cmos or lvttl) pins 0 and 1 of port 5 are overvoltage-tolerant pins individual control of input and output buffer enabling/disabling in addition to drive-strength modes hold mode for latching previous state (used for retaining the i/o state in deep sleep and hibernate modes) selectable slew rates for dv/dt-related noise control to improve emi the pins are organized in logical entities called ports, which are 8-bit in width. during power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. a multiplexing network known as a high-speed i/o matrix (hsiom) is used to multiplex between various signals that may connect to an i/o pin. pin locations for fixed-function peripherals are also fixed to reduce internal multi- plexing complexity (these sig nals do not go through the dsi network). dsi signals are not affected by this and any pin may be routed to any udb through the dsi network. data output and pin-state register s store, respectively, the values to be driven on the pins and the states of the pins themselves. every i/o pin can generate an interrupt if so enabled and each i/o port has an interrupt request (irq) and interrupt service routine (isr) vector associated with it (5 for psoc 4xx8_ble).
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 10 of 48 special-function peripherals lcd segment drive psoc 4xx8_ble has an lcd controller, which can drive up to four commons and up to 32 segments . it uses full digital methods to drive the lcd segments requiring no generation of internal lcd voltages. the two methods used are referred to as digital correlation and pwm. the digital correlation method modulates the frequency and levels of the common and segment signals to generate the highest rms voltage across a segment to light it up or to keep the rms signal zero. this method is good for stn displays but may result in reduced contrast with tn (cheaper) displays. the pwm method drives the panel with pwm signals to effec- tively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired lcd voltage. this method results in higher power consumption but can result in better results when driving tn displays. lcd operation is supported during deep sleep mode, refreshing a small display buffer (four bits ; one 32-bit register per port). capsense capsense is supported on all pins in psoc 4xx8_ble through a capsense sigma-delta (csd) block that can be connected to any pin through an analog mux bus that any gpio pin can be connected to via an analog switch. capsense function can thus be provided on any pin or group of pins in a system under software control. a component is provided for the capsense block to make it easy for the user. the shield voltage can be driven on another mux bus to provide liquid-tolerance capability. liquid tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. the capsense block has two idacs which can be used for general purposes if capsense is not being used (both idacs are available in that case) or if capsense is used without liquid tolerance (one idac is available).
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 11 of 48 pinouts ta b l e 1 shows the pin list for the psoc 4xx8_ble device. port 3 consis ts of the high-speed analog inputs for the sar mux. all pins support csd capsense and analog mux bus connections. table 1. psoc 4xx8_ble pin list (qfn package) pin name type description 1 vddd power 1.71-v to 5.5-v digital supply 2 xtal32o/p6.0 clock 32.768-khz crystal 3 xtal32i/p6.1 clock 32.768-khz crystal or external clock input 4 xres reset reset, active low 5 p4.0 gpio port 4 pin 0, lcd, csd 6 p4.1 gpio port 4 pin 1, lcd, csd 7 p5.0 gpio port 5 pin 0, lcd, csd 8 p5.1 gpio port 5 pin 1, lcd, csd 9 vssd ground digital ground 10 vddr power 1.9-v to 5.5-v radio supply 11 gant1 ground antenna shielding ground 12 ant antenna antenna pin 13 gant2 ground antenna shielding ground 14 vddr power 1.9-v to 5.5-v radio supply 15 vddr power 1.9-v to 5.5-v radio supply 16 xtal24i clock 24-mhz crystal or external clock input 17 xtal24o clock 24-mhz crystal 18 vddr power 1.9-v to 5.5-v radio supply 19 p0.0 gpio port 0 pin 0, lcd, csd 20 p0.1 gpio port 0 pin 1, lcd, csd 21 p0.2 gpio port 0 pin 2, lcd, csd 22 p0.3 gpio port 0 pin 3, lcd, csd 23 vddd power 1.71-v to 5.5-v digital supply 24 p0.4 gpio port 0 pin 4, lcd, csd 25 p0.5 gpio port 0 pin 5, lcd, csd 26 p0.6 gpio port 0 pin 6, lcd, csd 27 p0.7 gpio port 0 pin 7, lcd, csd 28 p1.0 gpio port 1 pin 0, lcd, csd 29 p1.1 gpio port 1 pin 1, lcd, csd 30 p1.2 gpio port 1 pin 2, lcd, csd 31 p1.3 gpio port 1 pin 3, lcd, csd 32 p1.4 gpio port 1 pin 4, lcd, csd 33 p1.5 gpio port 1 pin 5, lcd, csd 34 p1.6 gpio port 1 pin 6, lcd, csd 35 p1.7 gpio port 1 pin 7, lcd, csd 36 vdda power 1.71-v to 5.5-v analog supply 37 p2.0 gpio port 2 pin 0, lcd, csd 38 p2.1 gpio port 2 pin 1, lcd, csd 39 p2.2 gpio port 2 pin 2, lcd, csd
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 12 of 48 40 p2.3 gpio port 2 pin 3, lcd, csd 41 p2.4 gpio port 2 pin 4, lcd, csd 42 p2.5 gpio port 2 pin 5, lcd, csd 43 p2.6 gpio port 2 pin 6, lcd, csd 44 p2.7 gpio port 2 pin 7, lcd, csd 45 vref ref 1.024-v reference 46 vdda power 1.71-v to 5.5-v analog supply 47 p3.0 gpio port 3 pin 0, lcd, csd 48 p3.1 gpio port 3 pin 1, lcd, csd 49 p3.2 gpio port 3 pin 2, lcd, csd 50 p3.3 gpio port 3 pin 3, lcd, csd 51 p3.4 gpio port 3 pin 4, lcd, csd 52 p3.5 gpio port 3 pin 5, lcd, csd 53 p3.6 gpio port 3 pin 6, lcd, csd 54 p3.7 gpio port 3 pin 7, lcd, csd 55 vssa ground analog ground 56 vccd power regulated 1.8-v supply, connect to 1.3-f capacitor. 57 epad ground ground paddle for the qfn package table 2. psoc 4xx8_ble pin list (wlcsp package) pin name type description a1 nc nc do not connect a2 vref ref 1.024-v reference a3 vssa ground analog ground a4 p3.3 gpio port 3 pin 3, analog/digital/lcd/csd a5 p3.7 gpio port 3 pin 7, analog/digital/lcd/csd a6 vssd ground digital ground a7 vssa ground analog ground a8 vccd power regulated 1.8-v supply, connect to 1- f capacitor a9 vddd power 1.71-v to 5.5-v digital supply b1 nb no ball no ball b2 p2.3 gpio port 2 pin 3, analog/digital/lcd/csd b3 vssa ground analog ground b4 p2.7 gpio port 2 pin 7, analog/digital/lcd/csd b5 p3.4 gpio port 3 pin 4, analog/digital/lcd/csd b6 p3.5 gpio port 3 pin 5, analog/digital/lcd/csd b7 p3.6 gpio port 3 pin 6, analog/digital/lcd/csd b8 xtal32i/p6.1 clock 32.768-khz crystal or external clock input b9 xtal32o/p6.0 clock 32.768-khz crystal c1 nc nc do not connect table 1. psoc 4xx8_ble pin list (qfn package) (continued) pin name type description
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 13 of 48 c2 vssa ground analog ground c3 p2.2 gpio port 2 pin 2, analog/digital/lcd/csd c4 p2.6 gpio port 2 pin 6, analog/digital/lcd/csd c5 p3.0 gpio port 3 pin 0, analog/digital/lcd/csd c6 p3.1 gpio port 3 pin 1, analog/digital/lcd/csd c7 p3.2 gpio port 3 pin 2, analog/digital/lcd/csd c8 xres reset reset, active low c9 p4.0 gpio port 4 pin 0, analog/digital/lcd/csd d1 nc nc do not connect d2 p1.7 gpio port 1 pin 7, analog/digital/lcd/csd d3 vdda power 1.71-v to 5.5-v analog supply d4 p2.0 gpio port 2 pin 0, analog/digital/lcd/csd d5 p2.1 gpio port 2 pin 1, analog/digital/lcd/csd d6 p2.5 gpio port 2 pin 5, analog/digital/lcd/csd d7 vssd ground digital ground d8 p4.1 gpio port 4 pin 1, analog/digital/lcd/csd d9 p5.0 gpio port 5 pin 0, analog/digital/lcd/csd e1 nc nc do not connect e2 p1.2 gpio port 1 pin 2, analog/digital/lcd/csd e3 p1.3 gpio port 1 pin 3, analog/digital/lcd/csd e4 p1.4 gpio port 1 pin 4, analog/digital/lcd/csd e5 p1.5 gpio port 1 pin 5, analog/digital/lcd/csd e6 p1.6 gpio port 1 pin 6, analog/digital/lcd/csd e7 p2.4 gpio port 2 pin 4, analog/digital/lcd/csd e8 p5.1 gpio port 5 pin 1, analog/digital/lcd/csd e9 vssd ground digital ground f1 nc nc do not connect f2 vssd ground digital ground f3 p0.7 gpio port 0 pin 7, analog/digital/lcd/csd f4 p0.3 gpio port 0 pin 3, analog/digital/lcd/csd f5 p1.0 gpio port 1 pin 0, analog/digital/lcd/csd f6 p1.1 gpio port 1 pin 1, analog/digital/lcd/csd f7 vssr ground radio ground f8 vssr ground radio ground f9 vddr power 1.9-v to 5.5-v radio supply g1 nc nc do not connect g2 p0.6 gpio port 0 pin 6, analog/digital/lcd/csd g3 vddd power 1.71-v to 5.5-v digital supply g4 p0.2 gpio port 0 pin 2, analog/digital/lcd/csd g5 vssd ground digital ground table 2. psoc 4xx8_ble pin list (wlcsp package) (continued) pin name type description
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 14 of 48 high-speed i/o matrix (hsiom) is a group of high-speed switches that routes gpios to the resources inside the device. these resources include capsense, tcpwms, i 2 c, spi, uart, and lcd. hsiom_port_selx are 32-bit-wide registers that control the routing of gpios. each register controls one port; four dedicated bits are assigned to each gpio in the port. this provides up to 16 different optio ns for gpio routing as shown in ta b l e 3 . g6 vssr ground radio ground g7 vssr ground radio ground g8 gant ground antenna shielding ground g9 vssr ground radio ground h1 nc nc do not connect h2 p0.5 gpio port 0 pin 5, analog/digital/lcd/csd h3 p0.1 gpio port 0 pin 1, analog/digital/lcd/csd h4 xtal24o clock 24-mhz crystal h5 xtal24i clock 24-mhz crystal or external clock input h6 vssr ground radio ground h7 vssr ground radio ground h8 ant antenna antenna pin j1 nc nc do not connect j2 p0.4 gpio port 0 pin 4, analog/digital/lcd/csd j3 p0.0 gpio port 0 pin 0, analog/digital/lcd/csd j4 vddr power 1.9-v to 5.5-v radio supply j7 vddr power 1.9-v to 5.5-v radio supply j8 no connect ?? table 2. psoc 4xx8_ble pin list (wlcsp package) (continued) pin name type description table 3. hsiom port settings value description 0 firmware-controlled gpio 1 output is firmware-controlled, but output enable (oe) is controlled from dsi. 2 both output and oe are controlled from dsi. 3 output is controlled fr om dsi, but oe is firmware-controlled. 4 pin is a csd sense pin 5 pin is a csd shield pin 6 pin is connected to amuxa 7 pin is connected to amuxb 8 pin-specific active function #0 9 pin-specific active function #1 10 pin-specific active function #2 11 reserved 12 pin is an lcd common pin 13 pin is an lcd segment pin 14 pin-specific deep-sleep function #0 15 pin-specific deep-sleep function #1 table 3. hsiom port settings (continued) value description
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 15 of 48 the selection of peripheral function for different gpio pins is given in ta b l e 4 . table 4. port pin connections name analog digital gpio active #0 active #1 active #2 deep sleep #0 deep sleep #1 p0.0 comp0_inp gpio tcpwm0_p[3] scb1_uart_rx[1] ? scb1_i2c_sda[1] scb1_spi_mosi[1] p0.1 comp0_inn gpio tcpwm0_n[3] scb1_uart_tx[1] ? scb1_i2c_scl[1] scb1_spi_miso[1] p0.2 ? gpio tcpwm1_p[3] scb1_uart_rts[1] ? comp0_out[0] scb1_spi_ss0[1] p0.3 ? gpio tcpwm1_n[3] scb1_uart_cts[1] ? comp1_out[0] scb1_spi_sclk[1] p0.4 comp1_inp gpio tcpwm1_p[0] scb0_uart_rx[1] ext_clk[0]/ eco_out[0] scb0_i2c_sda[1] scb0_spi_mosi[1] p0.5 comp1_inn gpio tcpwm1_n[0] scb0_uart_tx[1] ? scb0_i2c_scl[1] scb0_spi_miso[1] p0.6 ? gpio tcpwm2_p[0] scb0_uart_rts[1] ? swdio[0] scb0_spi_ss0[1] p0.7 ? gpio tcpwm2_n[0] scb0_uart_cts[1] ? swdclk[0] scb0_spi_sclk[1] p1.0 ctbm1_oa0_inp gpio tcpwm0_p[1] ? ? comp0_out[1] wco_out[2] p1.1 ctbm1_oa0_inn gpio tcpwm0_n[1] ? ? comp1_out[1] scb1_spi_ss1 p1.2 ctbm1_oa0_out gpio tcpwm1_p[1] ? ? ? scb1_spi_ss2 p1.3 ctbm1_oa1_out gpio tcpwm1_n[1] ? ? ? scb1_spi_ss3 p1.4 ctbm1_oa1_inn gpio tcpwm2_p[1] scb0_uart_rx[0] ? scb0_i2c_sda[0] scb0_spi_mosi[1] p1.5 ctbm1_oa1_inp gpio tcpwm2_n[1] scb0_uart_tx[0] ? scb0_i2c_scl[0] scb0_spi_miso[1] p1.6 ctbm1_oa0_inp gpio tcpwm3_p[1] scb0_uart_rts[0] ? ? scb0_spi_ss0[1] p1.7 ctbm1_oa1_inp gpio tcpwm3_n[1] scb0_uart_cts[0] ? ? scb0_spi_sclk[1] p2.0 ctbm0_oa0_inp gpio ? ? ? ? scb0_spi_ss1 p2.1 ctbm0_oa0_inn gpio ? ? ? ? scb0_spi_ss2 p2.2 ctbm0_oa0_out gpio ? ? ? wakeup scb0_spi_ss3 p2.3 ctbm0_oa1_out gpio ? ? ? ? wco_out[1] p2.4 ctbm0_oa1_inn gpio ? ? ? ? ? p2.5 ctbm0_oa1_inp gpio ? ? ? ? ? p2.6 ctbm0_oa0_inp gpio ? ? ? ? ? p2.7 ctbm0_oa1_inp gpio ? ? ext_clk[1]/eco_out[ 1] ?? p3.0 sarmux_0 gpio tcpwm0_p[2] scb0_uart_rx[2] ? scb0_i2c_sda[2] ? p3.1 sarmux_1 gpio tcpwm0_n[2] scb0_uart_tx[2] ? scb0_i2c_scl[2] ? p3.2 sarmux_2 gpio tcpwm1_p[2] scb0_uart_rts[2] ? ? ? p3.3 sarmux_3 gpio tcpwm1_n[2] scb0_uart_cts[2] ? ? ? p3.4 sarmux_4 gpio tcpwm2_p[2] scb1_uart_rx[2] ? scb1_i2c_sda[2] ? p3.5 sarmux_5 gpio tcpwm2_n[2] scb1_uart_tx[2] ? scb1_i2c_scl[2] ? p3.6 sarmux_6 gpio tcpwm3_p[2] scb1_uart_rts[2] ? ? ? p3.7 sarmux_7 gpio tcpwm3_n[2] scb1_uart_cts[2] ? ? wco_out[0] p4.0 cmod gpio tcpwm0_p[0] scb1_uart_rts[0] ? ? scb1_spi_mosi[0] p4.1 ctank gpio tcpwm0_n[0] scb1_uart_cts[0] ? ? scb1_spi_miso[0] p5.0 ? gpio tcpwm3_p[0] scb1_uart_rx[0] extpa_en scb1_i2c_sda[0] scb1_spi_ss0[0] p5.1 ? gpio tcpwm3_n[0] scb1_uart_tx[0] ext_clk[2]/eco_out[ 2] scb1_i2c_scl[0] scb1_spi_sclk[0] p6.0_xtal32o ? gpio ? ? ? ? ? p6.1_xtal32i ? gpio ? ? ? ? ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 16 of 48 the possible pin connections are shown for a ll analog and di gital peripherals (except the radio, lcd, and csd blocks, which wer e shown in table 1 ). a typical system application co nnection diagram is shown in figure 7 . figure 7. system application connection diagram power the psoc 4xx8_ble device can be supplied from batteries with a voltage range of 1.9 v to 5.5 v by directly connecting to the digital supply (vddd), analog supply (vdda), and radio supply (vddr) pins. internal ldos in the device regulate the supply voltage to the required levels fo r different blocks. the device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation. analog circuits run directly from the analog supply (vdda) i nput. the device uses separate regulators for deep sleep and hibernate (lowered power supply and retention) modes to minimi ze the power consumption. the radio stops working below 1.9 v , but the device continues to function down to 1.71 v without rf. bypass capacitors must be used fr om vddx (x = a, d, or r) to ground. the typical practice for systems in this frequency range is to use a capacitor in the 1-f range in parallel with a smaller capacitor (for example, 0.1 f). note that these are simply rules of thumb and that, for critical ap plications, the pcb layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. swdio swdclk vddr vddd vddr vdda vdda vddr vddd c6 c1 1.0 uf u1 psoc 4xxx_ble 56-qfn vddd 1 xtal32o/p6.0 2 xtal32i/p6.1 3 xres 4 p4.0 5 p5.0 7 p5.1 8 vss 9 vddr 10 gant1 11 ant 12 gant2 13 vddr 14 p4.1 6 vddr 15 xtal24i 16 xtal24o 17 vddr 18 vddd 23 p0.0 19 p0.1 20 p0.2 21 p0.3 22 p0.4 24 p0.5 25 p0.6 26 p0.7 27 p1.0 28 p1.1 29 p1.2 30 p1.3 31 p1.4 32 p1.5 33 p1.6 34 p1.7 35 p2.0 37 p2.1 38 p2.2 39 p2.3 40 p2.4 41 p2.5 42 p2.6 43 p2.7 44 vref 45 vdda 46 p3.0 47 p3.1 48 p3.2 49 p3.3 50 p3.4 51 p3.5 52 p3.6 53 p3.7 54 vssa 55 vccd 56 vdda 36 epad 57 y2 32.768khz 1 2 c4 18 pf c3 36 pf c2 1.0 uf y1 24mhz 1 2 3 4 l1 antenna 1 1 2 2 c5 1.3 47 pf 24 pf power supply bypass capacitors vddd the internal bandgap may be bypassed with a 1-f to 10-f. vdda 0.1-f ceramic at each pin plus bulk capacitor 1-f to 10-f. vddr 0.1-f ceramic at each pin plus bulk capacitor 1-f to 10-f. vccd 1.3-f ceramic capacitor at the vccd pin. vref (optional) the internal bandgap may be bypassed with a 1-f to 10-f capacitor.
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 17 of 48 development support the psoc 4xx8_ble family has a rich set of documentation, development tools, and online resources to assist you during your development process. visit www.cypress.com/go/psoc4ble to find out more. documentation a suite of documentation supp orts the psoc 4xx8_ble family to ensure that you can find answ ers to your questions quickly. this section contains a list of some of the key documents. software user guide : a step-by-step guide for using psoc creator. the software user guide shows you how the psoc creator build process works in de tail, how to use source control with psoc creator, and much more. component datasheets : the flexibility of psoc allows the creation of new peripherals (components) long after the device has gone into production. component datasheets provide all of the information needed to select and use a particular component, including a functional description, api documen- tation, example code, and ac/dc specifications. application notes : psoc application notes discuss a particular application of psoc in depth; examples include creating standard and custom ble profiles. application notes often include example projects in addition to the application note document. technical reference manual : the technical reference manual (trm) contains all the technical detail you need to use a psoc device, including a complete de scription of all psoc registers. the trm is available in the documentation section at www.cypress.com/psoc4. online in addition to print documentation, the cypress psoc forums connect you with fellow psoc users and experts in psoc from around the world, 24 hours a day, 7 days a week. tools with industry standard cores, programming, and debugging interfaces, the psoc 4xx8_ble family is part of a development tool ecosystem. visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use psoc creator ide, supported third party compilers, programmers, debuggers, and development kits.
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 18 of 48 electrical specifications absolute maximum ratings device-level specifications all specifications are valid for ?40 c ? ta ? 85 c and tj ? 100 c, except where not ed. specifications are va lid for 1.71 v to 5.5 v, except where noted. note 1. usage above the absolute maximum conditions listed in tab l e 5 may cause permanent damage to the device. expos ure to absolute maximum conditions for extended periods of time may affect device reliabilit y. the maximum storage temperature is 150 c in compliance with jedec standard jesd2 2-a103, high temperature storage life. when used below absolute maximum conditions but a bove normal operating conditions, the device may not operate to specification. table 5. absolute maximum ratings [1] spec id# parameter description min typ max units details/ conditions sid1 v ddd_abs analog, digital, or radio supply relative to v ss (v ssd = v ssa ) ?0.5 ? 6 v absolute max sid2 v ccd_abs direct digital core voltage input relative to v ssd ?0.5 ? 1.95 v absolute max sid3 v gpio_abs gpio voltage ?0.5 ? v dd +0.5 v absolute max sid4 i gpio_abs maximum current per gpio ?25 ? 25 ma absolute max sid5 i gpio_injection gpio injection current, max for v ih > v ddd , and min for v il < v ss ?0.5 ? 0.5 ma absolute max, current injected per pin bid57 esd_hbm electrostatic discharge human body model 2200 ? ? v ? bid58 esd_cdm electrostatic discharge charged device model 500 ? ? v ? bid61 lu pin current for latch-up ?200 ? 200 ma ? table 6. dc specifications spec id# parameter description min typ max units details/ conditions sid6 v dd power supply input voltage (v dda = v ddd = v dd ) 1.8 ? 5.5 v with regulator enabled sid7 v dd power supply input voltage unregu- lated (v dda = v ddd = v dd ) 1.71 1.8 1.89 v internally unregulated supply sid8 v ddr radio supply voltage (radio on) 1.9 ? 5.5 v ? sid8a v ddr radio supply voltage (radio off) 1.71 ? 5.5 v ? sid9 v ccd digital regulator output voltage (for core logic) ?1.8? v ? sid10 c vccd digital regulator output bypass capacitor 1 1.3 1.6 f x5r ceramic or better active mode, v dd = 1.71 v to 5.5 v ? sid13 i dd3 execute from flash; cpu at 3 mhz ? 1.7 ? ma t = 25 c, v dd = 3.3 v sid14 i dd4 execute from flash; cpu at 3 mhz ? ? ? ma t = ?40 c to 85 c sid15 i dd5 execute from flash; cpu at 6 mhz ? 2.5 ? ma t = 25 c, v dd = 3.3 v sid16 i dd6 execute from flash; cpu at 6 mhz ? ? ? ma t = ?40 c to 85 c sid17 i dd7 execute from flash; cpu at 12 mhz ? 4 ? ma t = 25 c, v dd = 3.3 v sid18 i dd8 execute from flash; cpu at 12 mhz ? ? ? ma t = ?40 c to 85 c
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 19 of 48 sid19 i dd9 execute from flash; cpu at 24 mhz ? 7.1 ? ma t = 25 c, v dd = 3.3 v sid20 i dd10 execute from flash; cpu at 24 mhz ? ? ? ma t = ?40 c to 85 c sid21 i dd11 execute from flash; cpu at 48 mhz ? 13.4 ? ma t = 25 c, v dd = 3.3 v sid22 i dd12 execute from flash; cpu at 48 mhz ? ? ? ma t = ?40 c to 85 c sleep mode, v dd = 1.8 to 5.5 v sid23 i dd13 imo on ? ? ? ma t = 25 c, vdd = 3.3 v, sysclk = 3mhz sleep mode, v dd and v ddr = 1.9 to 5.5 v sid24 i dd14 eco on ???ma t = 25 c, vdd = 3.3 v, sysclk = 3 mhz deep sleep mode, v dd = 1.8 to 3.6 v sid25 i dd15 wdt with wco on ? 1.6 ? a t = 25 c, v dd = 3.3 v sid26 i dd16 wdt with wco on ? ? ? a t = ?40 c to 85 c deep sleep mode, v dd = 3.6 to 5.5 v sid27 i dd17 wdt with wco on ? ? ? a t = 25 c, v dd = 5 v sid28 i dd18 wdt with wco on ? ? ? a t = ?40 c to 85 c deep sleep mode, v dd = 1.71 to 1.89 v (regulator bypassed) sid29 i dd19 wdt with wco on ? ? ? a t = 25 c sid30 i dd20 wdt with wco on ? ? ? a t = ?40 c to 85 c deep sleep mode, v dd = 1.8 to 3.6 v sid31 i dd21 opamp on ? ? ? a t = 25 c, v dd = 3.3 v sid32 i dd22 opamp on ? ? ? a t = ?40 c to 85 c deep sleep mode, v dd = 3.6 to 5.5 v sid33 i dd23 opamp on ? ? ? a t = 25 c, v dd = 5 v sid34 i dd24 opamp on ? ? ? a t = ?40 c to 85 c deep sleep mode, v dd = 1.71 to 1.89 v (regulator bypassed) sid35 i dd25 opamp on ? ? ? a t = 25 c sid36 i dd26 opamp on ? ? ? a t = ?40 c to 85 c hibernate mode, v dd = 1.8 to 3.6 v sid37 i dd27 gpio and reset active ? 150 ? na t = 25 c, v dd = 3.3v sid38 i dd28 gpio and reset active ? ? ? na t = ?40 c to 85 c hibernate mode, v dd = 3.6 to 5.5 v sid39 i dd29 gpio and reset active ? ? ? na t = 25 c, v dd = 5 v sid40 i dd30 gpio and reset active ? ? ? na t = ?40 c to 85 c hibernate mode, v dd = 1.71 to 1.89 v (regulator bypassed) table 6. dc specifications (continued) spec id# parameter description min typ max units details/ conditions
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 20 of 48 sid41 i dd31 gpio and reset active ? ? ? na t = 25 c sid42 i dd32 gpio and reset active ? ? ? na t = ?40 c to 85 c stop mode, v dd = 1.8 to 3.6 v sid43 i dd33 stop mode current (v dd )?20?na t = 25 c, v dd = 3.3 v sid44 i dd34 stop mode current (v ddr ) ? 40 ?- na t = 25 c, v ddr = 3.3 v sid45 i dd35 stop mode current (v dd ) ? ? ? na t = ?40 c to 85 c sid46 i dd36 stop mode current (v ddr ) ???na t = ?40 c to 85 c, v ddr = 1.9 v to 3.6 v stop mode, v dd = 3.6 to 5.5 v sid47 i dd37 stop mode current (v dd ) ???na t = 25 c, v dd = 5 v sid48 i dd38 stop mode current (v ddr ) ???na t = 25 c, v ddr = 5 v sid49 i dd39 stop mode current (v dd ) ? ? ? na t = ?40 c to 85 c sid50 i dd40 stop mode current (v ddr ) ? ? ? na t = ?40 c to 85 c stop mode, v dd = 1.71 to 1.89 v (regulator bypassed) sid51 i dd41 stop mode current (v dd ) ???nat = 25 c sid52 i dd42 stop mode current (v dd ) ? ? ? na t = ?40 c to 85 c table 6. dc specifications (continued) spec id# parameter description min typ max units details/ conditions table 7. ac specifications spec id# parameter description min typ max units details/ conditions sid53 f cpu cpu frequency dc ? 48 mhz 1.71 v ?? v dd ?? 5.5 v sid54 t sleep wakeup from sleep mode ? 0 ? s guaranteed by characterization sid55 t deepsleep wakeup from deep sleep mode ? ? 25 s 24-mhz imo. guaranteed by characterization. sid56 t hibernate wakeup from hibernate mode ? ? 0.7 ms guaranteed by characterization sid57 t stop wakeup from stop mode ? ? 2.2 ms guaranteed by characterization
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 21 of 48 gpio note 2. v ih must not exceed v ddd + 0.2 v. table 8. gpio dc specifications spec id# parameter description min typ max units details/conditions sid58 v ih input voltage high threshold 0.7 v dd ? ? v cmos input sid59 v il input voltage low threshold ? ? 0.3 v dd v cmos input sid60 v ih lvttl input, v dd < 2.7 v 0.7 v dd ? - v ? sid61 v il lvttl input, v dd < 2.7 v ? ? 0.3 v dd v? sid62 v ih lvttl input, v dd >= 2.7 v 2.0 ? - v ? sid63 v il lvttl input, v dd >= 2.7 v ? ? 0.8 v ? sid64 v oh output voltage high level v dd ?0.6 ? ? v ioh = 4-ma at 3.3-v v dd sid65 v oh output voltage high level v dd ?0.5 ? ? v ioh = 1-ma at 1.8-v v dd sid66 v ol output voltage low level ? ? 0.6 v iol = 8-ma at 3.3-v v dd sid67 v ol output voltage low level ? ? 0.6 v iol = 4-ma at 1.8-v v dd sid68 v ol output voltage low level ? ? 0.4 v iol = 3-ma at 3.3-v v dd sid69 rpullup pull-up resistor 3.5 5.6 8.5 k ? ? sid70 rpulldown pull-down resistor 3.5 5.6 8.5 k ? ? sid71 i il input leakage current (absolute value) ? ? 2 na 25 c, v dd = 3.3 v sid72 i il_ctbm input leakage on ctbm input pins ? ? 4 na ? sid73 c in input capacitance ? ? 7 pf ? sid74 vhysttl input hysteresis lvttl 25 40 mv v dd > 2.7 v sid75 vhyscmos input hysteresis cmos 0.05 v dd ? ? mv ? sid76 idiode current through protection diode to v dd /v ss ? ? 100 a ? sid77 i tot_gpio maximum total source or sink chip current ? ? 200 ma ? table 9. gpio ac specifications spec id# parameter description min typ max units details/ conditions sid78 t risef rise time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25-pf sid79 t fallf fall time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25-pf sid80 t rises rise time in slow-strong mode 10 ? 60 ? 3.3-v v ddd , c load = 25-pf sid81 t falls fall time in slow-strong mode 10 ? 60 ? 3.3-v v ddd , c load = 25-pf sid82 f gpiout1 gpio fout; 3.3 v ? v dd ?? 5.5 v. fast-strong mode ??33mhz 90/10%, 25-pf load, 60/40 duty cycle sid83 f gpiout2 gpio fout; 1.7 v ?? v dd ?? 3.3 v. fast-strong mode ? ? 16.7 mhz 90/10%, 25-pf load, 60/40 duty cycle sid84 f gpiout3 gpio fout; 3.3 v ?? v dd ?? 5.5 v. slow-strong mode ??7mhz 90/10%, 25-pf load, 60/40 duty cycle sid85 f gpiout4 gpio fout; 1.7 v ?? v dd ?? 3.3 v. slow-strong mode ??3.5mhz 90/10%, 25-pf load, 60/40 duty cycle sid86 f gpioin gpio input operating frequency; 1.71 v ?? v dd ?? 5.5 v ? ? 48 mhz 90/10% v io
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 22 of 48 xres table 10. ovt gpio dc specifications (p5_0 and p5_1 only) spec id# parameter description min typ max units details/conditions sid71a i il input leakage current (absolute value), v ih > v dd ? ? 10 a 25 c, v dd = 0 v, v ih = 3.0 v sid66a v ol output voltage low level ? ? 0.4 v i ol = 20-ma, v dd > 2.9-v table 11. ovt gpio ac specifications (p5_0 and p5_1 only) spec id# parameter description min typ max units details/conditions sid78a t rise_ovfs output rise time in fast-strong mode 1.5 ? 12 ns 25-pf load, 10%?90%, v dd =3.3-v sid79a t fall_ovfs output fall time in fast-strong mode 1.5 ? 12 ns 25-pf load, 10%?90%, v dd =3.3-v sid80a t risss output rise time in slow-strong mode 10 ? 60 ns 25-pf load, 10%?90%, v dd =3.3-v sid81a t fallss output fall time in slow-strong mode 10 ? 60 ns 25-pf load, 10%?90%, v dd =3.3-v sid82a f gpiout1 gpio f out ; 3.3 v ? v dd 5.5 v fast-strong mode ??24mhz 90/10%, 25-pf load, 60/40 duty cycle sid83a f gpiout2 gpio f out ; 1.71 v ? v dd 3.3 v fast-strong mode ??16mhz 90/10%, 25-pf load, 60/40 duty cycle table 12. xres dc specifications spec id# parameter description min typ max units details/conditions sid87 v ih input voltage high threshold 0.7 v ddd ? ? v cmos input sid88 v il input voltage low threshold ? ? 0.3 v ddd v cmos input sid89 rpullup pull-up resistor 3.5 5.6 8.5 k ? ? sid90 c in input capacitance ? 3 ? pf ? sid91 v hysxres input voltage hysteresis ? 100 ? mv ? sid92 i diode current through protection diode to v ddd /v ss ??100a ? table 13. xres ac specifications spec id# parameter description min typ max units details/conditions sid93 t resetwidth reset pulse width 1 ? ? s ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 23 of 48 analog peripherals opamp table 14. opamp specifications spec id# parameter description min typ max units details/ conditions i dd (opamp block current. v dd = 1.8 v. no load) sid94 i dd_hi power = high ? 1000 1850 a ? sid95 i dd_med power = medium ? 500 950 a ? sid96 i dd_low power = low ? 250 350 a ? gbw (load = 20 pf, 0.1 ma. v dda = 2.7 v) sid97 gbw_hi power = high 6 ? ? mhz ? sid98 gbw_med power = medium 4 ? ? mhz ? sid99 gbw_lo power = low ? 1 ? mhz ? i out_max (v dda ? 2.7 v, 500 mv from rail) sid100 i out_max_hi power = high 10 ? ? ma ? sid101 i out_max_mid power = medium 10 ? ? ma ? sid102 i out_max_lo power = low ? 5 ? ma ? i out (v dda = 1.71 v, 500 mv from rail) sid103 i out_max_hi power = high 4 ? ? ma ? sid104 i out_max_mid power = medium 4 ? ? ma ? sid105 i out_max_lo power = low ? 2 ? ma ? sid106 v in charge pump on, v dda ? 2.7 v ?0.05 ? v dda ? 0.2 v ? sid107 v cm charge pump on, v dda ? 2.7 v ?0.05 ? v dda ? 0.2 v ? v out ( v dda ? 2.7 v) sid108 v out_1 power = high, i load =10 ma 0.5 ? v dda ? 0.5 v ? sid109 v out_2 power = high, i load =1 ma 0.2 ? v dda ? 0.2 v ? sid110 v out_3 power = medium, i load =1 ma 0.2 ? v dda ? 0.2 v ? sid111 v out_4 power = low, i load =0.1 ma 0.2 ? v dda ? 0.2 v ? sid112 v os_tr offset voltage, trimmed 1 0.5 1 mv high mode sid113 v os_tr offset voltage, trimmed ? 1 ? mv medium mode sid114 v os_tr offset voltage, trimmed ? 2 ? mv low mode sid115 v os_dr_tr offset voltage drift, trimmed ?10 3 10 v/c high mode sid116 v os_dr_tr offset voltage drift, trimmed ? 10 ? v/c medium mode sid117 v os_dr_tr offset voltage drift, trimmed ? 10 ? v/c low mode sid118 cmrr dc 70 80 ? db v ddd = 3.6 v sid119 psrr at 1 khz, 100-mv ripple 70 85 ? db v ddd = 3.6 v noise sid120 v n1 input referred, 1 hz?1 ghz, power = high ? 94 ? vrms ? sid121 v n2 input referred, 1-khz, power = high ? 72 ? nv/rthz ? sid122 v n3 input referred, 10-khz, power = high ? 28 ? nv/rthz ? sid123 v n4 input referred, 100-khz, power = high ? 15 ? nv/rthz ? sid124 c load stable up to maximum load. perfor- mance specs at 50 pf ? ? 125 pf ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 24 of 48 sid125 slew_rate cload = 50 pf, power = high, v dda ? 2.7 v 6? ? v/s ? sid126 t_op_wake from disable to enable, no external rc dominating ?300 ? s ? comp_mode (comparator mode; 50-mv drive, t rise = t fall (approx.) sid127 t pd1 response time; power = high ? 150 ? ns ? sid128 t pd2 response time; power = medium ? 400 ? ns ? sid129 t pd3 response time; power = low ? 2000 ? ns ? sid130 vhyst_op hysteresis ? 10 ? mv ? deep sleep (deep sleep mode operation is only guaranteed for v dda > 2.5 v) sid131 gbw_ds gain bandwidth product ? 50 ? khz ? sid132 idd_ds current ? 15 ? a ? sid133 vos_ds offset voltage ? 5 ? mv ? sid134 vos_dr_ds offset voltage drift ? 20 ? v/c ? sid135 vout_ds output voltage 0.2 ? v dd ?0.2 v ? sid136 vcm_ds common mode voltage 0.2 ? v dd ?1.8 v ? table 14. opamp specifications (continued) spec id# parameter description min typ max units details/ conditions note 3. ulp lcomp operating conditions: - v ddd 2.6 v-5.5 v for datasheet temp range < 0 c - v ddd 1.8 v-5.5 v for datasheet temp range 0 c table 15. comparator dc specifications [3] spec id# parameter description min typ max units details/conditions sid140 v offset1 input offset voltage, factory trim ? ? 10 mv ? sid141 v offset2 input offset voltage, custom trim ? ? 6 mv ? sid141a v offset3 input offset voltage, ultra-low-power mode ?12? mv v ddd 2.6 v for te m p < 0 c v ddd 1.8 v for te m p 0c sid142 v hyst hysteresis when enabled. common mode voltage range from 0 to vdd ?1 ? 10 35 mv ? sid143 v icm1 input common mode voltage in normal mode 0? v ddd ?0.1 v modes 1 and 2 sid144 v icm2 input common mode voltage in low power mode 0? v ddd v? sid145 v icm3 input common mode voltage in ultra low power mode 0? v ddd ?1.15 v v ddd 2.6 v for te m p < 0 c v ddd 1.8 v for te m p 0c sid146 cmrr common mode rejection ratio 50 ? ? db v ddd 2.7 v sid147 cmrr common mode rejection ratio 42 ? ? db v ddd 2.7 v sid148 i cmp1 block current, normal mode ? ? 400 a ? sid149 i cmp2 block current, low power mode ? ? 100 a ? sid150 i cmp3 block current in ultra low-power mode ? 6 ? a v ddd 2.6 v for te m p < 0 c v ddd 1.8 v for te m p 0c sid151 z cmp dc input impedance of comparator 35 ? ? m ? ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 25 of 48 temperature sensor sar adc note 4. ulp lcomp operating conditions: - v ddd 2.6 v-5.5 v for datasheet temp range < 0 c - v ddd 1.8 v-5.5 v for datasheet temp range 0 c table 16. comparator ac specifications [4] spec id# parameter description min typ max units details/ conditions sid152 t resp1 response time, normal mode, 50-mv overdrive ? 38 ? ns 50-mv overdrive sid153 t resp2 response time, low power mode, 50-mv overdrive ? 70 ? ns 50-mv overdrive sid154 t resp3 response time, ultra-low-power mode, 50-mv overdrive ? 2.3 ? s 200-mv overdrive v ddd 2.6 v for te m p < 0 c v ddd 1.8 v for te m p 0c table 17. temperature sensor specifications spec id# parameter description min typ max units details/conditions sid155 t sensacc temperature sensor accuracy ?5 1 5 c ?40 to +85 c table 18. sar adc dc specifications spec id# parameter description min typ max units details/conditions sid156 a_res resolution ? ? 12 bits ? sid157 a_chnis_s number of channels - single-ended ? ? 8 ? 8 full-speed sid158 a-chnks_d number of channels - differential ? ? 4 ? diff inputs use neighboring i/o sid159 a-mono monotonicity ? ? ? ? yes sid160 a_gainerr gain error ? ? 0.1 % with external reference. sid161 a_offset input offset voltage ? ? 2 mv measured with 1-v v ref sid162 a_isar current consumption ? ? 1 ma ? sid163 a_vins input voltage range - single-ended v ss ?v dda v? sid164 a_vind input voltage range - differential v ss ? v dda v? sid165 a_inres input resistance ? ? 2.2 k ? ? sid166 a_incap input capacitance ? ? 10 pf ? sid312 vrefsar trimmed inter nal reference to sar ?1 ? 1 % percentage of vbg (1.024-v)
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 26 of 48 csd table 19. sar adc ac specifications spec id# parameter description min typ max units details/ conditions sid167 a_psrr power supply rejection ratio 70 ? ? db measured at 1-v reference sid168 a_cmrr common mode rejection ratio 66 ? ? db ? sid169 a_samp sample rate ? ? 1 msps 806 ksps for psoc 41x8_ble devices sid313 fsarintref sar operating speed without external ref. bypass ? ? 100 ksps 12-bit resolution sid170 a_snr signal-to-noise ratio (snr) 65 ? ? db fin = 10 khz sid171 a_bw input bandwidth without aliasing ? ? a_samp/2 khz ? sid172 a_inl integral non linearity. v dd = 1.71 to 5.5 v, 1 msps ?1.7 ? 2 lsb vref = 1 v to v dd sid173 a_inl integral non linearity. v ddd = 1.71 to 3.6 v, 1 msps ?1.5 ? 1.7 lsb vref = 1.71 v to v dd sid174 a_inl integral non linearity. v dd = 1.71 to 5.5 v, 500 ksps ?1.5 ? 1.7 lsb vref = 1 v to v dd sid175 a_dnl differential non linearity. v dd = 1.71 to 5.5 v, 1 msps ?1 ? 2.2 lsb vref = 1 v to v dd sid176 a_dnl differential non linearity. v dd = 1.71 to 3.6 v, 1 msps ?1 ? 2 lsb vref = 1.71 v to v dd sid177 a_dnl differential non linearity. v dd = 1.71 to 5.5 v, 500 ksps ?1 ? 2.2 lsb vref = 1 v to v dd sid178 a_thd total harmonic distortion ? ? ?65 db fin = 10 khz table 20. csd block specifications spec id# parameter description min typ max units details/ conditions sid179 v csd voltage range of o peration 1.71 ? 5.5 v ? sid180 idac1 dnl for 8-bit resolution ?1 ? 1 lsb ? sid181 idac1 inl for 8-bit resolution ?3 ? 3 lsb ? sid182 idac2 dnl for 7-bit resolution ?1 ? 1 lsb ? sid183 idac2 inl for 7-bit resolution ?3 ? 3 lsb ? sid184 snr ratio of counts of finger to noise 5 ? ? ratio capacitance range of 9 to 35 pf, 0.1 pf sensitivity. radio is not operating during the scan sid185 i dac1_crt1 output current of idac1 (8 bits) in high range ? 612 ? a ? sid186 i dac1_crt2 output current of idac1 (8 bits) in low range ? 306 ? a ? sid187 i dac2_crt1 output current of idac2 (7 bits) in high range ? 305 ? a ? sid188 i dac2_crt2 output current of idac2 (7 bits) in low range ? 153 ? a ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 27 of 48 digital peripherals timer counter pulse width modulation (pwm) table 21. timer dc specifications spec id parameter description min typ max units details/conditions sid189 i tim1 block current consumption at 3 mhz ? ? 43 a 16-bit timer sid190 i tim2 block current consumption at 12 mhz ? ? 152 a 16-bit timer sid191 i tim3 block current consumption at 48 mhz ? ? 620 a 16-bit timer table 22. timer ac specifications spec id parameter description min typ max units details/conditions sid192 t timfreq operating frequency f clk ?48mhz ? sid193 t capwint capture pulse width (internal) 2 t clk ??ns ? sid194 t capwext capture pulse width (external) 2 t clk ??ns ? sid195 t timres timer resolution t clk ??ns ? sid196 t tenwidint enable pulse width (internal) 2 t clk ??ns ? sid197 t tenwidext enable pulse width (external) 2 t clk ??ns ? sid198 t timreswint reset pulse width (internal) 2 t clk ??ns ? sid199 t timresext reset pulse width (external) 2 t clk ??ns ? table 23. counter dc specifications spec id parameter description min typ max units details/conditions sid200 i ctr1 block current consumption at 3 mhz ? ? 43 a 16-bit counter sid201 i ctr2 block current consumption at 12 mhz ? ? 152 a 16-bit counter sid202 i ctr3 block current consumption at 48 mhz ? ? 620 a 16-bit counter table 24. counter ac specifications spec id parameter description min typ max units details/conditions sid203 t ctrfreq operating frequency f clk ?48mhz ? sid204 t ctrpwint capture pulse width (internal) 2 t clk ??ns ? sid205 t ctrpwext capture pulse width (external) 2 t clk ??ns ? sid206 t ctres counter resolution t clk ??ns ? sid207 t cenwidint enable pulse width (internal) 2 t clk ??ns ? sid208 t cenwidext enable pulse width (external) 2 t clk ??ns ? sid209 t ctrreswint reset pulse width (internal) 2 t clk ??ns ? sid210 t ctrreswext reset pulse width (external) 2 t clk ?? ns ? table 25. pwm dc specifications spec id parameter description min typ max units details/conditions sid211 i pwm1 block current consumption at 3 mhz ? ? 43 a 16-bit pwm sid212 i pwm2 block current consumption at 12 mhz ? ? 152 a 16-bit pwm sid213 i pwm3 block current consumption at 48 mhz ? ? 620 a 16-bit pwm
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 28 of 48 i 2 c lcd direct drive table 26. pwm ac specifications spec id parameter description min typ max units details/conditions sid214 t pwmfreq operating frequency f clk ?48mhz ? sid215 t pwmpwint pulse width (internal) 2 t clk ??ns ? sid216 t pwmext pulse width (external) 2 t clk ??ns ? sid217 t pwmkillint kill pulse width (internal) 2 t clk ??ns ? sid218 t pwmkillext kill pulse width (external) 2 t clk ??ns ? sid219 t pwmeint enable pulse width (internal) 2 t clk ??ns ? sid220 t pwmenext enable pulse width (external) 2 t clk ??ns ? sid221 t pwmreswint reset pulse width (internal) 2 t clk ??ns ? sid222 t pwmreswext reset pulse width (external) 2 t clk ??ns ? table 27. fixed i 2 c dc specifications spec id parameter description min typ max units details/conditions sid223 i i2c1 block current consumption at 100 khz ? ? 50 a? sid224 i i2c2 block current consumption at 400 khz ? ? 155 a? sid225 i i2c3 block current consumption at 1 mbps ? ? 390 a? sid226 i i2c4 i 2 c enabled in deep sleep mode ? ? 1.4 a? table 28. fixed i 2 c ac specifications spec id parameter description min typ max units details/conditions sid227 f i2c1 bit rate ? ? 1 mbps ? table 29. lcd direct drive dc specifications spec id parameter description min typ max units details/conditions sid228 i lcdlow operating current in low-power mode ? 17.5 ? a 16 4 small segment display at 50 hz sid229 c lcdcap lcd capacitance per segment/common driver ? 500 5000 pf ? sid230 lcd offset long-term segment offset ? 20 ? mv ? sid231 i lcdop1 lcd system operating current v bias = 5 v. ?2?ma 32 4 segments. 50 hz at 25 c sid232 i lcdop2 lcd system operating current. v bias = 3.3 v ?2?ma 32 4 segments 50 hz at 25 c table 30. lcd direct drive ac specifications spec id parameter description min typ max units details/conditions sid233 f lcd lcd frame rate 10 50 150 hz ? table 31. fixed uart dc specifications spec id parameter description min typ max units details/conditions sid234 i uart1 block current consumption at 100 kbps ? ? 55 a? sid235 i uart2 block current consumption at 1000 kbps ? ? 360 a?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 29 of 48 spi specifications memory table 32. fixed uart ac specifications spec id parameter description min typ max units details/conditions sid236 f uart bit rate ? ? 1 mbps ? table 33. fixed spi dc specifications spec id parameter description min typ max units details/conditions sid237 i spi1 block current consumption at 1 mbps ? ? 360 a ? sid238 i spi2 block current consumption at 4 mbps ? ? 560 a ? sid239 i spi3 block current consumption at 8 mbps ? ? 600 a ? table 34. fixed spi ac specifications spec id parameter description min typ max units details/conditions sid240 f spi spi operating frequency (master; 6x oversampling) ?? 8mhz ? table 35. fixed spi master mode ac specifications spec id parameter description min typ max units details/conditions sid241 t dmo mosi valid after sclock driving edge ? ? 18 ns ? sid242 t dsi miso valid before sclock capturing edge. full clock, late miso sampling used 20 ? ? ns full clock, late miso sampling sid243 t hmo previous mosi data hold time 0 ? ? ns referred to slave capturing edge table 36. fixed spi slave mode ac specifications spec id parameter description min typ max units details/conditions sid244 t dmi mosi valid before sclock capturing edge 40 ? ? ns ? sid245 t dso miso valid after sclock driving edge ? ? 42 + 3 t cpu ns ? sid246 t dso_ext miso valid after sclock driving edge in external clock mode ? ? 53 ns v dd < 3.0 v sid247 t hso previous miso data hold time 0 ? ? ns ? sid248 t sselsck ssel valid to first sck valid edge 100 ? ? ns ? table 37. flash dc specifications spec id parameter description min typ max units details/conditions sid249 v pe erase and program voltage 1.71 ? 5.5 v ? sid309 t ws48 number of wait states at 32?48 mhz 2? ? cpu execution from flash sid310 t ws32 number of wait states at 16?32 mhz 1? ? cpu execution from flash sid311 t ws16 number of wait states for 0?16 mhz 0? ? cpu execution from flash
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 30 of 48 system resources power-on-reset (por) note 5. it can take as much as 20 milliseconds to write to flash. du ring this time, the device should not be reset, or flash operatio ns will be interrupted and cannot be relied on to have completed. reset sources include the xres pin, softwa re resets, cpu lockup states and privilege violations, improper power supply levels, and watchdogs. make certain that these are not inadvertently activated. table 38. flash ac specifications spec id parameter description min typ max units details/conditions sid250 t rowwrite [5] row (block) write time (erase and program) ? ? 20 ms row (block) = 256 bytes sid251 t rowerase [5] row erase time ? ? 13 ms ? sid252 t rowprogram [5] row program time after erase ? ? 7 ms ? sid253 t bulkerase [5] bulk erase time (256 kb) ? ? 35 ms ? sid254 t devprog [5] total device program time ? ? 50 seconds for 256 kb sid255 f end flash endurance 100 k ? ? cycles ? sid256 f ret flash retention. t a ? 55 c, 100 k p/e cycles 20 ? ? years ? sid257 f ret2 flash retention. t a ? 85 c, 10 k p/e cycles 10 ? ? years ? table 39. por dc specifications spec id parameter description min typ max units details/conditions sid258 v riseipor rising trip voltage 0.80 ? 1.45 v ? sid259 v fallipor falling trip voltage 0.75 ? 1.40 v ? sid260 v iporhyst hysteresis 15 ? 200 mv ? table 40. por ac specifications spec id parameter description min typ max units details/conditions sid264 t ppor_tr ppor response time in active and sleep modes ??1s ? table 41. brown-out detect spec id# parameter description min typ max units details/ conditions sid261 v fallppor bod trip voltage in active and sleep modes 1.64 ? ? v ? sid262 v falldpslp bod trip voltage in deep sleep mode 1.4 ? ? v ? table 42. hibernate reset spec id# parameter description min typ max units details/ conditions sid263 v hbrtrip bod trip voltage in hibernate mode 1.1 ? ? v ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 31 of 48 voltage monitors swd interface internal main oscillator table 43. voltage monitor dc specifications spec id parameter description min typ max units details/conditions sid265 v lvi1 lvi_a/d_sel[3:0] = 0000b 1.71 1.75 1.79 v ? sid266 v lvi2 lvi_a/d_sel[3:0] = 0001b 1.76 1.80 1.85 v ? sid267 v lvi3 lvi_a/d_sel[3:0] = 0010b 1.85 1.90 1.95 v ? sid268 v lvi4 lvi_a/d_sel[3:0] = 0011b 1.95 2.00 2.05 v ? sid269 v lvi5 lvi_a/d_sel[3:0] = 0100b 2.05 2.10 2.15 v ? sid270 v lvi6 lvi_a/d_sel[3:0] = 0101b 2.15 2.20 2.26 v ? sid271 v lvi7 lvi_a/d_sel[3:0] = 0110b 2.24 2.30 2.36 v ? sid272 v lvi8 lvi_a/d_sel[3:0] = 0111b 2.34 2.40 2.46 v ? sid273 v lvi9 lvi_a/d_sel[3:0] = 1000b 2.44 2.50 2.56 v ? sid274 v lvi10 lvi_a/d_sel[3:0] = 1001b 2.54 2.60 2.67 v ? sid2705 v lvi11 lvi_a/d_sel[3:0] = 1010b 2.63 2.70 2.77 v ? sid276 v lvi12 lvi_a/d_sel[3:0] = 1011b 2.73 2.80 2.87 v ? sid277 v lvi13 lvi_a/d_sel[3:0] = 1100b 2.83 2.90 2.97 v ? sid278 v lvi14 lvi_a/d_sel[3:0] = 1101b 2.93 3.00 3.08 v ? sid279 v lvi15 lvi_a/d_sel[3:0] = 1110b 3.12 3.20 3.28 v ? sid280 v lvi16 lvi_a/d_sel[3:0] = 1111b 4.39 4.50 4.61 v ? sid281 lvi_idd block current ? ? 100 a ? table 44. voltage monitor ac specifications spec id parameter description min typ max units details/conditions sid282 t montrip voltage monitor trip time ? ? 1 s ? table 45. swd interface specifications spec id parameter description min typ max units details/conditions sid283 f_swdclk1 3.3 v ? v dd ? 5.5 v ? ? 14 mhz swdclk 1/3 cpu clock frequency sid284 f_swdclk2 1.71 v ? v dd ? 3.3 v ? ? 7 mhz swdclk 1/3 cpu clock frequency sid285 t_swdi_setup t = 1/f swdclk 0.25 t ? ? ns ? sid286 t_swdi_hold t = 1/f swdclk 0.25 t ? ? ns ? sid287 t_swdo_valid t = 1/f swdclk ? ? 0.5 t ns ? sid288 t_swdo_hold t = 1/f swdclk 1 ? ? ns ? table 46. imo dc specifications spec id parameter description min typ max units details/conditions sid289 i imo1 imo operating current at 48 mhz ? ? 1000 a ? sid290 i imo2 imo operating current at 24 mhz ? ? 325 a ? sid291 i imo3 imo operating current at 12 mhz ? ? 225 a ? sid292 i imo4 imo operating current at 6 mhz ? ? 180 a ? sid293 i imo5 imo operating current at 3 mhz ? ? 150 a ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 32 of 48 internal low-speed oscillator table 47. imo ac specifications spec id parameter description min typ max units details/conditions sid296 f imotol3 frequency variation from 3 to 48 mhz ??2% with api-called calibration sid297 f imotol3 imo startup time ? ? 12 s ? table 48. ilo dc specifications spec id parameter description min typ max units details/conditions sid298 i ilo2 ilo operating current at 32 khz ? 0.3 1.05 a ? table 49. ilo ac specifications spec id parameter description min typ max units details/conditions sid299 t startilo1 ilo startup time ? ? 2 ms ? sid300 f ilotrim1 32-khz trimmed frequency 15 32 50 khz ? table 50. external clock specifications spec id parameter description min typ max units details/conditions sid301 extclkfreq external clock input frequency 0 ? 48 mhz cmos input level only sid302 extclkduty duty cycle; measured at v dd/2 45 ? 55 % cmos input level only table 51. udb ac specifications spec id parameter description min typ max units details/conditions data path performance sid303 f max-timer max frequency of 16-bit timer in a udb pair ??48mhz ? sid304 f max-adder max frequency of 16-bit adder in a udb pair ??48mhz ? sid305 f max_crc max frequency of 16-bit crc/prs in a udb pair ??48mhz ? pld performance in udb sid306 f max_pld max frequency of 2-pass pld function in a udb pair ??48mhz ? clock to output performance sid307 t clk_out_udb1 prop. delay for clock in to data out at 25 c, typical ?15 ? ns ? sid308 t clk_out_udb2 prop. delay for clock in to data out, worst case ?25 ? ns ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 33 of 48 table 52. ble subsystem spec id# parameter description min typ max units details/ conditions rf receiver specification sid340 rxs, idle rx sensitivity with idle transmitter ? ?89 ? dbm ? sid340a rx sensitivity with idle transmitter excluding balun loss ? ?91 ? dbm guaranteed by design simulation sid341 rxs, dirty rx sensitivity with dirty transmitter ? ?87 ?70 dbm rf-phy specification (rcv-le/ca/01/c) sid342 rxs, highgain rx sensitivity in high-gain mode with idle transmitter ? ?91 ? dbm ? sid343 prxmax maximum input power ?10 ?1 ? dbm rf-phy specification (rcv-le/ca/06/c) sid344 ci1 co-channel interference, wanted signal at ?67 dbm and inter- ferer at frx ?921 db rf-phy specification (rcv-le/ca/03/c) sid345 ci2 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at frx 1 mhz ?315 db rf-phy specification (rcv-le/ca/03/c) sid346 ci3 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at frx 2 mhz ? ?29 ? db rf-phy specification (rcv-le/ca/03/c) sid347 ci4 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at frx 3 mhz ? ?39 ? db rf-phy specification (rcv-le/ca/03/c) sid348 ci5 adjacent channel interference wanted signal at ?67 dbm and interferer at image frequency (f image ) ? ?20 ? db rf-phy specification (rcv-le/ca/03/c) sid349 ci6 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at image frequency (f image 1mhz) ? ?30 ? db rf-phy specification (rcv-le/ca/03/c) sid350 obb1 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 30?2000 mhz ?30 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid351 obb2 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 2003?2399 mhz ?35 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid352 obb3 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 2484?2997 mhz ?35 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid353 obb4 out-of-band blocking, wanted signal a ?67 dbm and inter- ferer at f = 3000?12750 mhz ?30 ?27 ? dbm rf-phy specification (rcv-le/ca/04/c) sid354 imd intermodulation performance wanted signal at ?64 dbm and 1-mbps ble, third, fourth, and fifth offset channel ?50 ? ? dbm rf-phy specification (rcv-le/ca/05/c)
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 34 of 48 sid355 rxse1 receiver spurious emission 30 mhz to 1.0 ghz ? ? ?57 dbm 100-khz measurement bandwidth etsi en300 328 v1.8.1 sid356 rxse2 receiver spurious emission 1.0 ghz to 12.75 ghz ? ? ?47 dbm 1-mhz measurement bandwidth etsi en300 328 v1.8.1 rf transmitter specifications sid357 txp, acc rf power accuracy ? 4 ? db ? sid358 txp, range rf power control range ? 20 ? db ? sid359 txp, 0dbm output power, 0-db gain setting (pa7) ?0 ? dbm ? sid360 txp, max output power, maximum power setting (pa10) ?3 ? dbm ? sid361 txp, min output power, minimum power setting (pa1) ? ?18 ? dbm ? sid362 f2avg average frequency deviation for 10101010 pattern 185 ? ? khz rf-phy specification (trm-le/ca/05/c) sid363 f1avg average frequency deviation for 11110000 pattern 225 250 275 khz rf-phy specification (trm-le/ca/05/c) sid364 eo eye opening = ? f2avg/ ? f1avg 0.8 ? ? rf-phy specification (trm-le/ca/05/c) sid365 ftx, acc frequency accuracy ?150 ? 150 khz rf-phy specification (trm-le/ca/06/c) sid366 ftx, maxdr maximum frequency drift ?50 ? 50 khz rf-phy specification (trm-le/ca/06/c) sid367 ftx, initdr initial frequency drift ?20 ? 20 khz rf-phy specification (trm-le/ca/06/c) sid368 ftx, dr maximum drift rate ?20 ? 20 khz/ 50 s rf-phy specification (trm-le/ca/06/c) sid369 ibse1 in-band spurious emission at 2-mhz offset ? ? ?20 dbm rf-phy specification (trm-le/ca/03/c) sid370 ibse2 in-band spurious emission at 3-mhz offset ??-30dbm rf-phy specification (trm-le/ca/03/c) sid371 txse1 transmitter spurious emissions (average), <1.0 ghz ? ? -55.5 dbm fcc-15.247 sid372 txse2 transmitter spurious emissions (average), >1.0 ghz ? ? -41.5 dbm fcc-15.247 rf current specifications sid373 irx receive current in normal mode ? 18.7 ? ma ? sid373a irx_rf radio receive current in normal mode ? 16.4 ? ma measured at v ddr sid374 irx, highgain receive current in high-gain mode ? 21.5 ? ma ? sid375 itx, 3dbm tx current at 3-dbm setting (pa10) ? 20 ? ma ? sid376 itx, 0dbm tx current at 0-dbm setting (pa7) ? 16.5 ? ma ? table 52. ble subsystem (continued) spec id# parameter description min typ max units details/ conditions
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 35 of 48 sid376a itx_rf, 0dbm radio tx current at 0 dbm setting (pa7) ? 15.6 ? ma measured at v ddr sid376b itx_rf, 0dbm radio tx current at 0 dbm excluding balun loss ? 14.2 ? ma guaranteed by design simulation sid377 itx,-3dbm tx current at ?3-dbm setting (pa4) ? 15.5 ? ma ? sid378 itx,-6dbm tx current at ?6-dbm setting (pa3) ? 14.5 ? ma ? sid379 itx,-12dbm tx current at ?12-dbm setting (pa2) ? 13.2 ? ma ? sid380 itx,-18dbm tx current at ?18-dbm setting (pa1) ? 12.5 ? ma ? sid380a iavg_1sec, 0dbm average current at 1-second ble connection interval ? 17.1 ? a txp: 0 dbm; 20-ppm master and slave clock accuracy. sid380b iavg_4sec, 0dbm average current at 4-second ble connection interval ?6.1 ? a txp: 0 dbm; 20-ppm master and slave clock accuracy. general rf specifications sid381 freq rf operating frequency 2400 ? 2482 mhz ? sid382 chbw channel spacing ? 2 ? mhz ? sid383 dr on-air data rate ? 1000 ? kbps ? sid384 idle2tx ble.idle to ble. tx transition time ? 120 140 s ? sid385 idle2rx ble.idle to ble. rx transition time ? 75 120 s ? rssi specifications sid386 rssi, acc rssi accuracy ? 5 ? db ? sid387 rssi, res rssi resolution ? 1 ? db ? sid388 rssi, per rssi sample period ? 6 ? s ? table 52. ble subsystem (continued) spec id# parameter description min typ max units details/ conditions table 53. eco specifications spec id# parameter description min typ max units details/ conditions sid389 f eco crystal frequency ? 24 ? mhz ? sid390 f tol frequency tolerance ?50 ? 50 ppm ? sid391 esr equivalent series resistance ? ? 60 ? ? sid392 pd drive level ? ? 100 w ? sid393 t start1 startup time (fast charge on) ? ? 850 s ? sid394 t start2 startup time (fast charge off) ? ? 3 ms ? sid395 c l load capacitance ? 8 ? pf ? sid396 c0 shunt capacitance ? 1.1 ? pf ? sid397 i eco operating current ? 1400 ? a ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 36 of 48 table 54. wco specifications spec id# parameter description min typ max units details/ conditions sid398 f wco crystal frequency ? 32.768 ? khz ? sid399 ftol frequency tolerance ? 50 ? ppm ? sid400 esr equivalent se ries resistance ? 50 ? k ? ? sid401 pd drive level ? ? 1 w ? sid402 t start startup time ? ? 500 ms ? sid403 c l crystal load capacitance 6 ? 12.5 pf ? sid404 c0 crystal shunt capacitance ? 1.35 ? pf ? sid405 i wco1 operating current (high-power mode) ?? 8a ? sid406 i wco2 operating current (low-power mode) ??2.6a ?
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 37 of 48 ordering information the psoc 4xx8_ble part numbers and features are listed in ta b l e 5 5 . table 55. psoc 4xxx8_ble part numbers mpn features package max cpu speed (mhz) ble subsystem flash (kb) sram (kb) udb opamp (ctbm) capsense tmg (gestures) direct lcd drive 12-bit sar adc lp comparators tcpwm blocks scb blocks pwms (using udbs) i2s (using udb) gpio cy8c4127lqi-bl473 24 ? 12816?2??? 806 ksps 2 4 2 not applicable 36 qfn cy8c4127lqi-bl453 24 ? 128 16 ? 2 ? ? ? 806 ksps 2 4 2 36 qfn CY8C4127LQI-BL483 24 ? 128 16 ? 2 ? ? ? 806 ksps 2 4 2 36 qfn cy8c4127lqi-bl493 24 ? 128 16 ? 2 ??? 806 ksps 2 4 2 36 qfn cy8c4127fni-bl483 24 ? 128 16 ? 2 ? ? ? 806 ksps 2 4 2 36 wlcsp cy8c4127fni-bl493 24 ? 128 16 ? 2 ??? 806 ksps 2 4 2 36 wlcsp cy8c4128lqi-bl443 24 ? 256 32????? 806 ksps - 4 2 na ? 36 qfn cy8c4128fni-bl443 24 ? 256 32????? 806 ksps - 4 2? ? 36 csp cy8c4128lqi-bl473 24 ? 256 32 ? 2??? 806 ksps 2 4 2? ? 36 qfn cy8c4128fni-bl473 24 ? 256 32 ? 2??? 806 ksps 2 4 2? ? 36 csp cy8c4128lqi-bl453 24 ? 256 32 ? 2 ? ?? 806 ksps 2 4 2? ? 36 qfn cy8c4128fni-bl453 24 ? 256 32 ? 2 ? ?? 806 ksps 2 4 2? ? 36 csp cy8c4128lqi-bl483 24 ? 256 32 ? 2 ? ? ? 806 ksps 2 4 2? ? 36 qfn cy8c4128fni-bl483 24 ? 256 32 ? 2 ? ? ? 806 ksps 2 4 2? ? 36 csp cy8c4128lqi-bl493 24 ? 256 32 ? 2 ? ? ? 806 ksps 2 4 2? ? 36 qfn cy8c4128fni-bl493 24 ? 256 32 ? 2 ? ? ? 806 ksps 2 4 2? ? 36 csp cy8c4247lqi-bl473 48 ? 1281644??? 1 msps 242 4 ? 36 qfn cy8c4247lqi-bl453 48 ? 128 16 4 4 ? ?? 1 msps 242 4 ? 36 qfn cy8c4247lqi-bl463 48 ? 1281644?? ? 1 msps 2 4 2 4 ? 36 qfn cy8c4247lqi-bl483 48 ? 128 16 4 4 ? ? ? 1 msps 2 4 2 4 ? 36 qfn cy8c4247lqi-bl493 48 ? 128 16 4 4 ??? 1 msps 2 4 2 4 ? 36 qfn cy8c4247fni-bl483 48 ? 128 16 4 4 ? ? ? 1 msps 2 4 2 4 ? 36 wlcsp cy8c4247fni-bl493 48 ? 128 16 4 4 ??? 1 msps 2 4 2 4 ? 36 wlcsp cy8c4248lqi-bl473 48 ? 256 32 44??? 1 msps 2 4 2 4 ? 36 qfn cy8c4248fni-bl473 48 ? 256 32 44??? 1 msps 2 4 2 4 ? 36 csp cy8c4248lqi-bl453 48 ? 256 32 44 ? ?? 1 msps 2 4 2 4 ? 36 qfn cy8c4248fni-bl453 48 ? 256 32 44 ? ?? 1 msps 2 4 2 4 ? 36 csp cy8c4248lqi-bl463 48 ? 256 32 44?? ? 1 msps 2 4 2 4 ? 36 qfn cy8c4248fni-bl463 48 ? 256 32 44?? ? 1 msps 2 4 2 4 ? 36 csp cy8c4248lqi-bl483 48 ? 256 32 44 ? ? ? 1 msps 2 4 2 4 ? 36 qfn cy8c4248fni-bl483 48 ? 256 32 4 4 ? ? ? 1 msps 2 4 2 4 ? 36 csp cy8c4248fli-bl483 48 ? 256 32 4 4 ? ? ? 1 msps 2 4 2 4 ? 36 thin csp cy8c4248lqi-bl493 48 ? 256 32 44 ? ? ? 1 msps 2 4 2 4 ? 36 qfn cy8c4248fni-bl493 48 ? 256 32 4 4 ? ? ? 1 msps 2 4 2 4 ? 36 csp
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 38 of 48 psoc 4 devices follow the part numbering convention described in the following table. all fields are single-character alphanume ric (0, 1, 2, ?, 9, a,b, ?, z) unless stated otherwise. ordering code definitions the field values are listed in the following table: architecture cypress prefix family within architecture speed grade flash capacity package code temperature range attributes code 4: psoc 4 4: 48mhz 8 : 256 kb lq : qfn i : industrial example cy8c 4 a e d c bfy x -z 2 : 4200 family cy8 c xyz : attributes field description values meaning cy8c cypress prefix 4 architecture 4 psoc 4 a family within architecture 1 4100-ble family 2 4200-ble family b cpu speed 2 24 mhz 4 48 mhz c flash capacity 8, 7 256, 128 kb de package code fn wlcsp lq qfn fl thin wlcsp f temperature range i industrial xyz attributes code 000-999 code of feature set in specific family
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 39 of 48 packaging table 56. package characteristics parameter description conditions min typ max units t a operating ambient temperature ? ?40 25.00 105 c t j operating junction temperature ? ?40 ? 100 c t ja package ? ja (56-pin qfn) ? ? 16.9 ? c/watt t jc package ? jc (56-pin qfn) ? ? 9.7 ? c/watt t ja package ? ja (76-ball wlcsp) ? ? 16.6 ? c/watt t jc package ? jc (76-ball wlcsp) ? ? 0.19 ? c/watt t ja package ? ja (76-ball thin wlcsp) ? ? 20.9 ? c/watt t jc package ? jc (76-ball thin wlcsp) ? ? 0.17 ? c/watt table 57. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 56-pin qfn 260 c 30 seconds 76-ball wlcsp and thin wlcsp 260 c 30 seconds table 58. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 56-pin qfn msl 3 76-ball wlcsp and thin wlcsp msl 1 table 59. package details spec id package description 001-58740 rev. *c 56-pin qfn 7.0 mm 7.0 mm 0.6 mm 001-96603 rev. *a 76-ball wlcsp 4.04 mm 3.87 mm 0.55 mm 002-10658, rev. ** 76-ball thin wlcsp 4.04 mm 3.87 mm 0.4 mm
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 40 of 48 figure 8. 56-pin qfn 7 7 0.6 mm the center pad on the qfn package should be connected to ground (vss) for best mechanical, thermal, and electrical performance. 1. hatch area is solderable exposed pad notes: 2. based on ref jedec # mo-248 3. all dimensions are in millimeters side view top view bottom view 001-58740 *c
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 41 of 48 wlcsp compatibility the psoc 4xxx_ble family has products with 128 kb (16kb sram) and 256 kb (32kb sr am) flash. package pin-outs and sizes are identical for the 56-pin qfn package but are di fferent in one dimension for the 68-ball wlcsp. the 256kb flash product has an extra column of balls which are required for mechanical integrity purposes in the chip-scale pac kage. with consideration for this difference, the land pattern on the pcb may be designed such that either product may be used with n o change to the pcb design. figure 9 shows the 128kb and 256 kb flash csp packages. figure 9. 128kb and 256 kb flash csp packages the rightmost column of (all nc, no connect) balls in the 256 k ble wlcsp is for mechanical integrity purposes. the package is thus wider (3.2 mm versus 2.8 mm). all ot her dimensions are identical . cypress will provide layout symbols for pcb layout. the scheme in figure 9 is implemented to design the pcb for the 256k ble package with the appropriate space requirements thus allowing use of either package at a later time without redesigning the printed circuit board. 128k ble 256k ble connected pads nc pads package center pack boundary fiducial for 128k fiducial for 256k
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 42 of 48 figure 10. 76-ball wlcsp package outline n is the number of populated solder ball positions for matrix when there is an even number of solder balls in the outer row, when there is an odd number of solder balls in the outer row, define the position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. "e" represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a solder ball position designation per jep95, section 3, spp-020. "+" indicates the theoretical center of depopulated solder a1 corner to be identified by chamfer, laser or ink mark 8. 7. 6. notes: 5. 4. 3. 2. 1. all dimensions are in millimeters. sd b ee ed me n 0.23 0.381 bsc 0.40 bsc 0.40 bsc 0.26 76 9 0.29 dimensions d1 md e1 e d a a1 symbol 0.18 min. - 3.20 bsc 3.20 bsc 9 4.04 bsc 3.87 bsc nom. - 0.55 0.24 max. se 0.321 bsc 0.21 metalized mark, indentation or other means. "sd" = ed/2 and "se" = ee/2. plane parallel to datum c. "sd" or "se" = 0. size md x me. balls. jedec specification no. ref : n/a 9. pin #1 mark a b j h g f e d c b a 987654321 j h g f e d c b a 9 8 7 6 5 4 3 2 1 d e top view side view bottom view e1 d1 76x?b 5 ?0.06 c m c ?0.03 m ab c a1 0.05 c 0.10 c detail a detail a ed ee se sd 7 6 6 a 001-96603 *b
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 43 of 48 figure 11. 76-ball thin wlcsp package outline n is the number of populated solder ball positions for matrix when there is an even number of solder balls in the outer row, when there is an odd number of solder balls in the outer row, define the position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. "e" represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a solder ball position designation per jep95, section 3, spp-020. "+" indicates the theoretical center of depopulated solder a1 corner to be identified by chamfer, laser or ink mark 8. 7. 6. notes: 5. 4. 3. 2. 1. all dimensions are in millimeters. sd b ee ed me n 0.22 0.381 0.40 bsc 0.40 bsc 0.25 76 9 0.28 dimensions d1 md e1 e d a a1 symbol 0.072 min. - 3.20 bsc 3.20 bsc 9 4.04 bsc 3.87 bsc nom. - 0.40 0.088 max. se 0.321 0.08 metalized mark, indentation or other means. "sd" = ed/2 and "se" = ee/2. plane parallel to datum c. "sd" or "se" = 0. size md x me. balls. pin #1 mark a b j h g f e d c b a 987654321 j h g f e d c b a 9 8 7 6 5 4 3 2 1 d e top view side view bottom view e1 d1 76x?b 5 ?0.06 c m c ?0.03 m ab c a1 0.05 c 0.10 c detail a detail a ed ee se sd 7 6 6 a 002-10658 **
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 44 of 48 acronyms table 60. acronyms used in this document acronym description abus analog local bus adc analog-to-digital converter ag analog global ahb amba (advanced microcontroller bus archi- tecture) high-performance bus, an arm data transfer bus alu arithmetic logic unit amuxbus analog mu ltiplexer bus api application programming interface apsr application program status register arm ? advanced risc machine, a cpu architecture atm automatic thump mode bw bandwidth can controller area network, a communications protocol cmrr common-mode rejection ratio cpu central processing unit crc cyclic redundancy check, an error-checking protocol dac digital-to-analog converter, see also idac, vdac dfb digital filter block dio digital input/output, gpio with only digital capabilities, no analog. see gpio. dmips dhrystone million instructions per second dma direct memory access, see also td dnl differential nonlinearity, see also inl dnu do not use dr port write data registers dsi digital system interconnect dwt data watchpoint and trace ecc error correcting code eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference emif external memory interface eoc end of conversion eof end of frame epsr execution program status register esd electrostatic discharge etm embedded trace macrocell fir finite impulse resp onse, see also iir fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output, applies to a psoc pin hvi high-voltage interrupt, see also lvi, lvd ic integrated circuit idac current dac, see also dac, vdac ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol iir infinite impulse response, see also fir ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo inl integral nonlinearity, see also dnl i/o input/output, see also gpio, dio, sio, usbio ipor initial power-on reset ipsr interrupt program status register irq interrupt request itm instrumentation trace macrocell lcd liquid crystal display lin local interconnect network, a communications protocol. lr link register lut lookup table lvd low-voltage detect, see also lvi lvi low-voltage interrupt, see also hvi lvttl low-voltage transistor-transistor logic mac multiply-accumulate mcu microcontroller unit miso master-in slave-out nc no connect nmi nonmaskable interrupt nrz non-return-to-zero nvic nested vectored interrupt controller nvl nonvolatile latch, see also wol opamp operational amplifier pal programmable array logic, see also pld table 60. acronyms us ed in this document (continued) acronym description
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 45 of 48 pc program counter pcb printed circuit board pga programmable gain amplifier phub peripheral hub phy physical layer picu port interrupt control unit pla programmable logic array pld programmable logic device, see also pal pll phase-locked loop pmdd package material declaration data sheet por power-on reset pres precise power-on reset prs pseudo random sequence ps port read data register psoc ? programmable system-on-chip? psrr power supply rejection ratio pwm pulse-width modulator ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rtl register transfer language rtr remote transmission request rx receive sar successive approximation register sc/ct switched capaci tor/continuous time scl i 2 c serial clock sda i 2 c serial data s/h sample and hold sinad signal to noise and distortion ratio sio special input/output, gpio with advanced features. see gpio. soc start of conversion sof start of frame spi serial peripheral interface, a communications protocol sr slew rate sram static random access memory sres software reset swd serial wire debug, a test protocol table 60. acronyms used in this document (continued) acronym description swv single-wire viewer td transaction descriptor, see also dma thd total harmonic distortion tia transimpedance amplifier trm technical reference manual ttl transistor-transistor logic tx transmit uart universal asynchronous transmitter receiver, a communications protocol udb universal digital block usb universal serial bus usbio usb input/output, psoc pins used to connect to a usb port vdac voltage dac, see also dac, idac wdt watchdog timer wol write once latch, see also nvl wres watchdog timer reset xres external reset i/o pin xtal crystal table 60. acronyms us ed in this document (continued) acronym description
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 46 of 48 document conventions units of measure table 61. units of measure symbol unit of measure c degrees celsius db decibel ff femto farad hz hertz kb 1024 bytes kbps kilobits per second khr kilohour khz kilohertz k ? kilo ohm ksps kilosamples per second lsb least significant bit mbps megabits per second mhz megahertz m ? mega-ohm msps megasamples per second a microampere f microfarad h microhenry s microsecond v microvolt w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm pf picofarad ppm parts per million ps picosecond s second sps samples per second sqrthz square root of hertz vvolt
preliminary psoc ? 4: psoc 4xx8_ble family datasheet document number: 001-94624 rev. *l page 47 of 48 revision history description title: psoc ? 4: psoc 4xx8_ble family datasheet programmable system-on-chip (psoc ? ) document number: 001-94624 revision ecn orig. of change submission date description of change *d 4792956 skar 06/ 10/2015 initial release *e 4922509 skar 09/17/2015 updated bluetooth version to 4.2. updated link layer features. updated max values for tcpwm dc specifications. updated ordering code definitions. updated package temperature r ange to ?40 c to 105 c. removed errata. *f 4992761 kisb 11/03/2015 updated the following specs: icmp1: from 280 ua to 400 ua icmp2: from 50 ua to100 ua ii2c1: from10.5 ua to 50 ua ii2c2: from 135 ua to 155 ua ii2c3: from 310 ua to 390ua ilcdlow: from 5 ua to 17.5ua iuart1: from 9 ua to 55ua lvi_idd: from 10 ua to 100 ua rxs, idle (sid340): from -90 dbm to -89 dbm rxs, idle (sid340a): from -92 dbm to -91 dbm rxs, highgain: from -92 dbm to -91 dbm iavg_4sec, 0 dbm: from 5.7 ua to 6.25 ua ieco: from 600 ua to 1400 ua voffset2: from 4 mv to 6 mv idd15: from1.5 ua to 1.6 ua vhyst (sid142): added "common mode voltage range? to description iwco2: changed spec limit to 2.6 a. *g 5094462 rlos 01/20/2016 added more information and psoc creator sections. *h 5129256 wka 02/09/2016 added thin wlcsp description and part number. *i 5133828 wka 02/16/2016 reordered the part numbers and removed internal references in ordering infor- mation . *j 5177483 marw 03/16/2016 updated conditions for sid141a, sid145, sid150, and sid154. *k 5266203 wka 05/10/2016 updated block diagram . updated gap features and sm features in ble radio and subsystem . updated sar adc system diagram . updated c3 and c4 values in system application connection diagram . updated values for sid56, sid380a, and sid380b. *l 5713202 gnkk 04/26/2017 updated the cypress logo. updated the 76-ball wlcsp package diagram. updated sales, solutions, and legal information .
document number: 001-94624 rev. *l revised april 26, 2017 page 48 of 48 preliminary psoc ? 4: psoc 4xx8_ble family datasheet ? cypress semiconductor corporation 2014-2017. this document is the property of cypress semiconductor corporation and its subsi diaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the r ight to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not lim ited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of an y product or circuit described in this document. any informati on provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly d esign, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as crit ical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support de vices or systems, other medical devices or systems (including r esuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or syste m, or to affect its safety or effectiv eness. cypress is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or relate d to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete li st of cypress trademarks, visit cypress.com. other names and bran ds may be claimed as property of their respective owners.. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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